Full Adder Circuit With Reused Signals and Lower Input Capacitance
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Solution Overview
Problem
Existing full adder circuits in CMOS technology have high transistor count and input capacitance, leading to increased power consumption and computation delays due to the dependency of sum and carry-out calculations, which affects the area occupancy and performance.
Innovation Solution
A compact full adder design is implemented with a first, second, and third stage, where reused signals from the first stage are used to generate both the sum and carry-out signals, reducing the number of transistors receiving primary inputs and employing transistor sharing to minimize footprint and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If sum and carry-out are implemented with dependent computation in existing CMOS full adder, then the circuit structure is straightforward, but the number of transistors receiving primary inputs increases, leading to higher input capacitance and power consumption
Solution Approach 1:
The full adder is divided into three distinct stages: first stage generates intermediate signals from primary inputs, second stage generates sum signal from intermediate signals, and third stage generates carry-out signal from intermediate signals. This segmentation allows independent computation paths that reduce the number of transistors directly receiving primary inputs, thereby reducing input capacitance and power consumption while maintaining structural clarity.
Solution Approach 2:
The first stage performs preliminary computation to generate intermediate signals (such as XOR and XNOR results) before the sum and carry-out calculations. These pre-computed intermediate signals are then reused in subsequent stages, eliminating the need for redundant primary input connections in later stages and reducing overall input capacitance.
2Reliability
If more transistors receive primary inputs to implement sum and carry-out, then the computation is more robust, but input capacitance and delays increase
Solution Approach 1:
By segmenting the computation into three stages with clear data flow, the circuit maintains robust computation through systematic signal processing while reducing the fan-out of primary inputs. Each stage processes specific intermediate signals rather than directly consuming multiple primary inputs, reducing capacitive loading and propagation delay.
Solution Approach 2:
Intermediate signals generated in the first stage serve as mediators between primary inputs and the final sum/carry-out outputs. These intermediate signals carry the necessary computational information to subsequent stages without requiring direct connections from primary inputs, thereby reducing input capacitance and computation delay while maintaining computational reliability.
3Adaptability or versatility
If a larger number of transistors are used in the full adder, then the circuit can handle more complex computations, but the area occupancy increases
Solution Approach 1:
The three-stage architecture segments the full adder functionality into distinct computational blocks, each handling specific operations. This segmentation enables efficient resource utilization where intermediate signals are reused across stages, reducing the total transistor count needed compared to a monolithic design while maintaining full adder functionality and adaptability.
Solution Approach 2:
The intermediate signals generated in the first stage serve multiple purposes: they are used by both the second stage (for sum calculation) and the third stage (for carry-out calculation). This multi-functionality of intermediate signals reduces redundant transistor instances and optimizes area occupancy while preserving the circuit's computational versatility.
Data Source
AI summary
Examples of compact, high performance full adder circuits and methods of forming and operating the same are provided. In an example, a full adder comprises a first stage, a second stage and a third stage. The first stage has a first output at which a first reused signal is generated and a second output at which a second reused signal is generated. The second stage has a first reused signal input to which the first reused signal is applied, a second reused signal input to which the second reused signal is applied, and a sum output at which a sum signal is generated. The third stage has a third reused signal input to which the first reused signal is applied, a fourth reused signal input to which the second reused signal is applied, and a carry-out output at which a carry-out signal is generated. In some examples, the first stage includes a transistor stack and an inverter that share a transistor.