Split-Loop Digital Phase-Frequency Detector for Fast Lock and Low Jitter
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Solution Overview
Problem
Conventional digital phase-locked loops (DPLLs) face challenges in achieving low jitter and fast locking due to the need for large delay chains, which result in high power consumption and complexity, while bang-bang phase detectors provide low jitter but at the cost of long settling times.
Innovation Solution
A digital phase-frequency detector is implemented using a ring oscillator with a time-to-digital converter and a bang-bang phase-frequency detector, allowing for low jitter and fast locking by combining coarse and fine acquisition feedback loops, with a compact ring oscillator design that maintains low power consumption and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large delay chain is used to provide a large dynamic range for the TDC, then the measurement precision is improved, but the device complexity and power consumption increase
Solution Approach 1:
The delay chain is divided into multiple segments with different delay ranges. A first portion handles coarse delay measurement while a second portion handles fine delay measurement, allowing each segment to be optimized for its specific range rather than requiring one large delay chain to cover the entire dynamic range.
Solution Approach 2:
The delay chain segments are dynamically selected based on the input signal characteristics. The system switches between different delay chain portions depending on whether coarse or fine adjustment is needed, enabling adaptive optimization of the measurement range and precision.
2Measurement precision
If a large delay chain is used to provide a large dynamic range for the TDC, then the measurement precision is improved, but the power consumption increases
Solution Approach 1:
The delay chain is divided into multiple segments with different delay ranges. A first portion handles coarse delay measurement while a second portion handles fine delay measurement, allowing each segment to be optimized for its specific range rather than requiring one large delay chain to cover the entire dynamic range.
Solution Approach 2:
The delay chain segments are dynamically selected based on the input signal characteristics. The system switches between different delay chain portions depending on whether coarse or fine adjustment is needed, enabling adaptive optimization of the measurement range and precision.
3Device complexity
If a bang-bang phase detector is used to reduce complexity and power consumption, then the device complexity and power consumption are reduced, but the settling time increases
Solution Approach 1:
The phase detection and adjustment process is segmented into two stages: a coarse acquisition phase that quickly brings the system near lock, and a fine acquisition phase that achieves precise locking. This segmentation allows the use of simpler logic in each stage while maintaining fast overall settling time.
Solution Approach 2:
The system dynamically switches between different control modes during acquisition. Initially, a faster coarse adjustment mode is used to quickly reduce the phase error, then transitions to a finer adjustment mode for precise locking, optimizing both speed and accuracy throughout the settling process.
4Device complexity
If a bang-bang phase detector is used to reduce complexity and power consumption, then the device complexity and power consumption are reduced, but the measurement precision deteriorates
Solution Approach 1:
The delay chain is divided into multiple segments with different delay ranges. A first portion handles coarse delay measurement while a second portion handles fine delay measurement, allowing each segment to be optimized for its specific range rather than requiring one large delay chain to cover the entire dynamic range.
Solution Approach 2:
The delay chain segments are dynamically selected based on the input signal characteristics. The system switches between different delay chain portions depending on whether coarse or fine adjustment is needed, enabling adaptive optimization of the measurement range and precision.
Data Source
AI summary
A digital phase-frequency detector characterizes a delay between two input clock signals using a ring oscillator. A cycle count of a ring oscillator signal circulating through a loop in the ring oscillator during the delay provides a coarse measurement of the delay. A phase of the ring oscillator signal in the loop at the end of the delay provides a fine measurement of the delay. A digital phase-locked loop may control an oscillation frequency of a digitally-controlled oscillator responsive to the fine measurement of the delay and control a division within a clock divider responsive to the coarse measurement of the delay.