FMA Mantissa Rounding with Merged 2's Complement Logic

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Solution Overview

Problem

Current floating-point arithmetic processing, particularly in fused multiply-add (FMA) operations, faces inefficiencies due to delays in 1's complement operations and separate rounding and 2's complement steps, which impact performance and precision in handling floating-point numbers.

Innovation Solution

The implementation of a method and device that includes an incrementor and rounding select circuit to manage unrounded mantissa values, incorporating a multiplexor to choose between incremented and non-incremented values based on a 2's complement signal, and a system that normalizes and rounds mantissa values efficiently, merging 2's complement and rounding operations to reduce delays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate rounding and 2's complement steps are used, then the operations can be performed independently, but the processing time increases due to multiple sequential steps

Engineering Contradiction:

Improveaccuracy of floating-point arithmeticVSAvoidprocessing delay

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent merges the rounding operation and 2's complement operation into a single unified circuit that performs both functions simultaneously. The rounding select circuit receives the unrounded mantissa, round bit, and 2's complement signal, then produces the rounded result in one step rather than requiring separate sequential operations, thereby reducing processing delay while maintaining accuracy

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent prepares the mantissa value in advance by generating both the incremented and non-incremented versions before the final selection is needed. The incrementor circuit pre-computes the incremented value, and the rounding select circuit is ready to choose between the incremented and non-incremented values based on the round bit and 2's complement signal, eliminating wait time during the critical path

Inventive Principle:

Principle #10Preliminary action

2Device complexity

If 1's complement operations are performed separately, then the logic can be simplified, but the overall processing speed decreases due to additional operation delays

Engineering Contradiction:

Improvelogic circuit complexityVSAvoidprocessing speed

Core Design Contradiction:

Device complexityVSSpeed

Solution Approach 1:

The patent combines the 1's complement operation with the rounding operation in a single integrated circuit. The rounding select circuit performs the 1's complement (by selecting the incremented value when a 2's complement signal is asserted) simultaneously with the rounding decision, eliminating the need for a separate 1's complement operation stage and thereby increasing processing speed without significantly increasing logic complexity

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20230214179A1Floating point fused multiply add with merged 2's complement and rounding

Publication Date: 2023.07.06 TEXAS INSTRUMENTS INC

AI summary

A method includes receiving an unrounded mantissa value and a round bit associated with the unrounded mantissa value. The method also includes receiving a 2's complement signal that indicates whether the unrounded mantissa value results from a 1's complement operation. The method includes incrementing the unrounded mantissa value to provide an incremented value. The unrounded mantissa value is a non-incremented value. The method further includes providing one of the incremented value or non-incremented value as a rounded mantissa value responsive to the 2's complement signal.