Memory Test Circuit Using Shared I/O Ports and Output Buffering
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Solution Overview
Problem
Existing memory device test circuits require a large number of input/output ports from the test machine, leading to resource wastage and increased testing costs.
Innovation Solution
The memory device incorporates a test mode selection unit, block selection unit, and output buffer that dynamically enable or disable input/output ports based on test mode selection signals, allowing for reduced port usage and efficient resource sharing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each memory device occupies dedicated input/output ports for testing, then testing reliability is improved, but test resource utilization deteriorates and testing costs increase
Solution Approach 1:
Multiple memory devices share common input/output ports through the output buffer, which multiplexes data from multiple storage modules through a reduced number of ports. This merging approach maintains testing reliability through proper signal management while dramatically improving test resource utilization by reducing the number of required ports from 204 to a much smaller number.
Solution Approach 2:
The output buffer serves multiple functions: it acts as a data output interface during normal operation and as a test data multiplexer during testing. This multi-functionality allows the same hardware structure to serve both operational and testing purposes, improving resource utilization without compromising testing reliability.
2Reliability
If multiple input/output ports are used for testing, then test coverage is improved, but device complexity increases
Solution Approach 1:
The output buffer acts as an intermediary between the multiple storage modules and the reduced set of input/output ports. It manages the complexity of routing data from multiple sources through fewer channels, maintaining comprehensive test coverage while reducing the visible complexity at the external interface level.
Solution Approach 2:
The test mode selection unit dynamically configures the output buffer's operation mode based on test requirements. This dynamic reconfiguration allows the same hardware to adapt to different test scenarios, maintaining comprehensive test coverage while avoiding the need for separate dedicated test circuits for each scenario.
3Measurement precision
If dedicated input/output ports are allocated for each memory device, then testing accuracy is improved, but resource waste increases
Solution Approach 1:
The output buffer merges data paths from multiple storage modules into a shared set of input/output ports, reducing resource waste while maintaining testing accuracy through proper signal management and timing control. This eliminates the need for dedicated ports for each device, reducing resource allocation from 204 ports to a much smaller number.
Data Source
AI summary
The present disclosure provides a memory device, wherein: an address latch can output a block selection control signal according to a block selection enable signal; a test mode selection unit can output a test mode selection signal according to a test mode selection instruction signal; a block selection unit outputs a block selection signal according to a mode selection signal and a block selection enable signal; when the memory enters a first test mode according to the test mode selection signal, an output buffer disables some of the input/output ports, and sequentially outputs the first input/output data and the second input/output data through un-disabled the input/output ports. The memory device according to the present disclosure can occupy less input/output ports of a test machine.