Semiconductor Memory ECS Timing Control for Accurate Refresh Counting
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Solution Overview
Problem
The generation of an ECS command signal based on a self-refresh command is lacking an external clock, leading to inaccuracies in counting and affecting the performance of semiconductor memory devices like DRAM, as complete error check and scrub operations cannot be reliably performed within the required time frame.
Innovation Solution
A control circuit is introduced with a timing control circuit that performs counting based on a first clock signal, generating an ECS flag signal when a preset condition is met, allowing the command control circuit to generate an ECS command signal accurately, ensuring timely completion of error check and scrub operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If the Self-Refresh command is used without an external clock, then the memory can operate autonomously, but the counting of refresh commands becomes inaccurate leading to ECS command generation errors
Solution Approach 1:
The patent introduces an external clock signal as an intermediary to mediate between the autonomous Self-Refresh operation and the accurate counting requirement. The external clock serves as a reference that enables precise counting of refresh commands while allowing the memory to maintain autonomous operation through the Self-Refresh command.
2Measurement precision
If the Auto-Refresh command is used with external clock, then accurate counting can be performed, but the system complexity increases due to clock signal requirements
Solution Approach 1:
The patent enables the memory system to self-service by using the existing external clock that is already present for other operations. The Self-Refresh command leverages this existing clock resource to perform accurate counting without requiring additional dedicated clock circuits or increasing overall system complexity.
3Ease of operation
If ECS command generation is performed without accurate timing, then the memory can maintain simple operation, but errors occur during error check and scrub operations
Solution Approach 1:
The patent implements a feedback mechanism where the external clock signal provides continuous timing information to the control circuit. This feedback enables the system to maintain simple operation while ensuring accurate ECS command generation by constantly referencing the clock signal for timing and counting operations.
Data Source
AI summary
Provided are a control circuit, a control method, and a semiconductor memory. The control circuit includes a timing control module and a command control module. An output terminal of the timing control module is connected to an input terminal of the command control module. The timing control module is configured to receive a first clock signal, perform counting based on the first clock signal, generate an error check and scrub (ECS) flag signal, and send the ECS flag signal to the command control module. The ECS flag signal is in a valid state when a counting value meets a preset condition. The command control module is configured to receive the ECS flag signal, obtain a refresh command signal when the ECS flag signal is in the valid state, and generate an ECS command signal based on the refresh command signal.