Serial Latching Array for In-Memory Arithmetic Speed
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Solution Overview
Problem
The miniaturization of integrated circuits poses challenges in design and manufacturing, requiring stricter specifications and improved reliability, particularly in ensuring efficient and reliable storage and computational operations.
Innovation Solution
A storage device with an array of latching units connected through inter-unit transmission gates, operating in various modes to perform arithmetic operations as a finite state machine, utilizing pulse operations to change states efficiently and improve computational speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Weight of moving object
If miniaturization of integrated circuits is pursued, then device size is reduced and power consumption is lowered, but design and manufacturing specifications become stricter and reliability challenges increase
Solution Approach 1:
The integrated circuit is divided into multiple storage units, each comprising serially connected latching units that can operate independently. This segmentation allows each unit to be miniaturized while maintaining reliable operation through modular design, where failures in one unit do not propagate to others.
Solution Approach 2:
Inter-unit transmission gates are introduced as intermediary components between adjacent latching units within storage units and between storage units. These transmission gates control signal flow and isolation, enabling reliable data transfer and state maintenance even as device dimensions are reduced, thereby addressing reliability challenges in miniaturized designs.
2Length of moving object
If miniaturization of integrated circuits is pursued, then device size is reduced, but design and manufacturing specifications become stricter
Solution Approach 1:
The circuit is segmented into standardized storage units with identical latching unit structures. This modular approach allows design optimization at the unit level while simplifying manufacturing, as the same components can be replicated across the device, reducing the impact of miniaturization on manufacturing precision requirements.
Solution Approach 2:
Each latching unit is designed as a universal building block that can function in multiple contexts (within different storage units, in different positions). This universality reduces design complexity and manufacturing specification stringency, as the same standardized components are used throughout the miniaturized device.
3Reliability
If conventional storage and computational operations are used, then device functionality is maintained, but computational speed and efficiency are limited
Solution Approach 1:
Storage and computational functions are merged within the same latching units and storage units. The latching units can maintain stored data states while also participating in arithmetic operations through controlled state transitions. This integration eliminates the need for separate storage and computation operations, significantly improving computational speed and efficiency while maintaining operational reliability.
Solution Approach 2:
Arithmetic operations are performed through periodic pulse signals that control state transitions in the latching units. By using synchronized periodic actions across multiple storage units, the system achieves concurrent arithmetic operations, enhancing computational throughput while maintaining reliable state management through rhythmic control signals.
4Ease of operation
If conventional sequential operations are used, then operational simplicity is maintained, but computational efficiency is reduced
Solution Approach 1:
The system uses periodic pulse operations to control state transitions in latching units. This periodic control mechanism maintains operational simplicity through standardized timing signals while enabling concurrent arithmetic operations across multiple storage units, thereby improving computational efficiency without complicating the control interface.
Solution Approach 2:
The latching units incorporate feedback mechanisms where the state of one latching unit influences the operation of adjacent units through inter-unit transmission gates. This feedback enables coordinated arithmetic operations across the storage array while maintaining ease of operation through automatic state propagation, eliminating the need for complex external control logic.
Data Source
AI summary
A method includes setting each latching unit in an array of latching units to a forward-connection mode for a duration of a first time period while each inter-unit transmission switch in a plurality of inter-unit transmission switches is at a connected state, and after the first time period, setting each latching unit in the array of latching units to a latch mode and setting each inter-unit transmission switch to a disconnected state. The method also includes setting each latching unit in the array of latching units to a backward-connection mode for a duration of a second time period while each inter-unit transmission switch is at a connected state, and after the second time period, setting each latching unit in the array of latching units to a latch mode and setting each inter-unit transmission switch to a disconnected state.