DLL Edge Combiner With Matched Loads for Precise Clock Locking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional Digital Locked Loops (DLLs) suffer from imprecision in output clock generation due to varying loads presented by edge combiners for different delay line outputs, leading to false lock conditions and inefficiencies in locking mechanisms.
Innovation Solution
A DLL circuit design that includes a delay line with multiple stages, a control circuit to adjust delays, and an edge combiner with logic gates configured to present equal schematic loads, allowing for precise phase alignment and frequency matching without false locks, utilizing a lock assist mode to quickly achieve and maintain lock conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional edge combiners are used to generate output clock from multiple delay line outputs, then the DLL can operate with simple structure, but the output clock becomes imprecise due to different loads for different delay line outputs
Solution Approach 1:
The patent applies local quality by making each delay line output drive an equal load. The edge combiner is designed so that each delay line output (e.g., Q0-Q3) presents the same schematic load (equal number of logic gate inputs), ensuring uniform propagation delays and precise output clock generation. This local uniformity in load distribution directly resolves the precision issue while maintaining structural simplicity.
2Device complexity
If the delay line presents different loads to different outputs, then the edge combiner structure is simple, but false lock conditions occur and locking reliability deteriorates
Solution Approach 1:
The patent ensures each delay line output drives an equal load through the edge combiner design. Specifically, each output (Q0-Q3) connects to the same number of logic gate inputs (two AND gate inputs each), creating uniform loading conditions. This prevents false lock conditions by ensuring accurate phase detection and reliable locking, directly improving locking reliability without increasing structural complexity.
3Device complexity
If unequal loads are presented by edge combiner to delay line outputs, then device structure is simpler, but propagation delay variations increase
Solution Approach 1:
The patent achieves uniform propagation delay by ensuring each delay line output presents an equal load. The edge combiner configuration where each output drives exactly two AND gate inputs creates identical loading conditions for all delay line stages. This local uniformity in load distribution minimizes propagation delay variations and ensures precise timing, directly addressing the manufacturing precision issue.
Data Source
AI summary
A DLL circuit that has a programmable output frequency is provided. The DLL circuit uses a single delay line to produce the multiple frequencies. In various embodiments, the delay line is configured to receive an input clock defining an input clock period. The delay line comprises delay stages, each configured to generate a corresponding output clock having a phase relative to the input clock based on a delay of the delay line. In those embodiments, a control circuit is configured to change the delay of the delay line so as to cause a phase difference between the input clock and a sensed output clock to be substantially equal to the input clock period. An edge combiner is configured to generate a DLL output clock based on the output clocks of the delay stages and presents an equal schematic load for each of the output clocks of the delay stages.