Dual-Fuse eFuse Circuit for Reliable Low-Power Programming
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Solution Overview
Problem
Conventional efuse units face issues with programming reliability due to incorrect logical values outputted by Sense Amplifiers (SA) when fuses are not properly blown or have insufficient resistance, leading to increased power consumption and area requirements.
Innovation Solution
The efuse unit incorporates two fuses connected in series with three NMOS transistors, allowing simultaneous programming and compensating for abnormal fuses during reading operations, reducing voltage and current requirements while ensuring correct outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional efuse unit uses one fuse and one NMOS control transistor, then the device complexity is low, but the programming reliability deteriorates due to incorrect logical output values
Solution Approach 1:
The efuse unit is segmented into two separate fuse links (first fuse link and second fuse link) instead of using a single fuse. This segmentation allows the system to evaluate multiple fuse states independently and perform logical operations on their results, thereby improving programming reliability while maintaining reasonable device complexity
Solution Approach 2:
The patent combines two fuse links with three NMOS transistors into a single integrated efuse unit structure. This merging approach allows the unit to achieve improved reliability through redundant fuse evaluation while controlling overall device complexity by integrating the components into a unified circuit architecture
2Area of stationary object
If the efuse unit uses conventional single fuse design, then the area occupied is small, but the power consumption increases due to higher programming voltage and current requirements
Solution Approach 1:
By segmenting the programming task across two fuse links, each fuse can be programmed with lower individual power requirements. The segmented approach distributes the power consumption across multiple lower-power operations rather than requiring one high-power operation, thus reducing overall power consumption while occupying similar area
Solution Approach 2:
The patent changes the programming parameters by using a multi-fuse structure that enables lower programming voltage and current per fuse. This parameter change allows the system to achieve the same reliability goal with reduced power consumption, as the distributed fuse structure reduces the stress and power requirements on each individual fuse element
3Reliability
If conventional efuse uses double bit working mode to improve reliability, then the programming reliability improves, but the device complexity and area increase
Solution Approach 1:
The patent merges the functionality of two separate efuse units into a single integrated unit by combining two fuse links with three shared NMOS transistors. This merging achieves the reliability benefits of dual-bit mode while reducing device complexity by eliminating redundant control transistor instances and integrating the evaluation logic into a unified structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances programming reliability, reduces power consumption, and minimizes the overall area by utilizing a backup fuse mechanism and shared NMOS transistors, ensuring accurate reading operations even with suboptimal fuse resistance.
Implementation Method 1
Efuse belongs to a One-Time Programmable (OTP) memory, which is based on the principle of electromigration (EM) and achieves programming functions by blowing a fuse
Data Source
AI summary
The present invention discloses an efuse unit, including a first fuse, a second fuse, a first NMOS, a second NMOS and a third NMOS. One end of the first fuse serves as a Q1 port, and the other end is connected to drain end of the third NMOS and the first NMOS. One end of the second fuse serves as a Q2 port and is short-circuited to a source end of the third NMOS, and the other end is connected to a drain end of the second NMOS. Agate end of the third NMOS serves as an RDWL port. A gate end of the first NMONS serves as a WLC port. A gate end of the second NMOS serves as a WL port. The present invention can improve the correctness of the reading operation, reduce the voltage required for the programming operation, reduce the programming current.