Clock Duty-Cycle Correction During Low-Power Reactivation
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Solution Overview
Problem
Existing duty-cycle correction methods in electronic devices fail to maintain accurate clock signal duty-cycles during operation, especially when the device transitions to low-power modes or is reactivated, leading to distorted clock signals and potential operational issues.
Innovation Solution
Incorporating a clock detector to disable duty-cycle correction when the input clock signal is disabled, allowing error signals to reset and ensuring accurate duty-cycle regulation upon reactivation, using an integrator circuit, amplifier circuit, and electrically controllable switch to maintain corrected clock signals within a few clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If duty-cycle correction is continuously applied, then clock signal duty-cycle accuracy is improved, but error signal saturation occurs during low-power modes
Solution Approach 1:
The clock detector detects the disabled state of the input clock signal in advance and proactively disables the duty-cycle correction circuit before error signal saturation can occur. This preliminary action prevents the harmful effect from developing while maintaining the ability to quickly resume correction upon reactivation.
Solution Approach 2:
The clock detector continuously monitors the state of the input clock signal and provides feedback to control the enable signal for the duty-cycle correction circuit. This feedback mechanism ensures the correction circuit is disabled during low-power modes and reenabled upon reactivation, preventing error saturation while maintaining duty-cycle accuracy during active operation.
2Reliability
If duty-cycle correction is disabled during low-power modes, then error signal saturation is prevented, but duty-cycle accuracy is lost during operation
Solution Approach 1:
The duty-cycle correction circuit's operational state is dynamically adjusted based on the clock signal state. The circuit is enabled during active operation to maintain duty-cycle accuracy and disabled during low-power modes to prevent error saturation. This dynamic adaptation allows the system to optimize performance for different operational conditions.
Solution Approach 2:
The clock detector provides continuous feedback about the clock signal state to control the enable signal, creating a dynamic system that automatically switches between correction and protection modes based on operational conditions, resolving the contradiction between maintaining accuracy and preventing saturation.
3Measurement precision
If duty-cycle correction resumes after low-power mode, then operational accuracy is restored, but clock period loss occurs during reactivation
Solution Approach 1:
The error signal is reset to zero in advance upon detection of clock reactivation, preparing the duty-cycle correction circuit for immediate accurate operation. This preliminary reset action eliminates the need for extended recovery periods, allowing the system to restore duty-cycle accuracy within a single clock cycle.
4Measurement precision
If complex correction circuits are used, then duty-cycle accuracy is improved, but device complexity increases
Solution Approach 1:
The clock detector serves as an intermediary component that simplifies the overall system by automatically managing the enable signal based on clock signal state. This intermediary prevents error saturation without requiring complex protection circuits, maintaining duty-cycle accuracy while minimizing device complexity through a straightforward detection-and-control mechanism.
Data Source
AI summary
Apparatuses and methods for correcting a duty-cycle of a clock signal are disclosed. An apparatus includes a duty-cycle adjuster, a circuit, and a clock detector. The duty-cycle adjuster is configured to receive an input clock signal and correct a duty-cycle of a corrected clock signal relative to an input duty-cycle of the input clock signal. The circuit is configured to control corrections made to the duty-cycle of the corrected clock signal by the duty-cycle adjuster. The clock detector is configured to disable the corrections made to the duty-cycle of the corrected clock signal responsive to a detection that the input clock signal is disabled.