Booth Multiplier Circuit for Faster Compute-in-Memory Accumulation
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Solution Overview
Problem
Implementing Booth multiplication in compute-in-memory (CIM) technology is hindered by the time-consuming nature of bit-serial operations and the requirement for multiple stages to generate partial sums before producing a final product, leading to increased latency and decreased computing speed.
Innovation Solution
A Booth multiplier is designed for CIM that employs Booth encoding and multi-cycle partial product generation, reducing hardware complexity and chip area by using a Booth encoder to convert input data into Booth encoded signals, which are then processed using multiplexers and adders to compute partial sums over several cycles, rather than generating all partial products sequentially.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If bit-serial operations are used for CIM processing, then hardware complexity is reduced, but computation time increases significantly
Solution Approach 1:
The patent divides the multiplication process into segments by generating partial products in a systematic sequence rather than requiring all partial products to be generated before accumulation. This segmentation allows intermediate results to be processed incrementally, reducing the overall computation time while maintaining the simplicity of bit-serial operations.
Solution Approach 2:
The patent performs preliminary actions by pre-computing and storing partial products in memory cells before the final accumulation step. This allows the multiplication process to overlap computation and storage operations, effectively reducing the critical path delay without requiring complex parallel hardware.
2Measurement precision
If all partial sums are generated in sequence before final addition, then computation accuracy is maintained, but processing speed decreases
Solution Approach 1:
The patent performs preliminary computation of partial products and stores them in memory cells before the final accumulation. This allows the system to maintain full computational accuracy while overlapping the generation of partial products with the accumulation process, thereby improving processing speed without sacrificing precision.
Solution Approach 2:
The patent introduces dynamic operation modes that allow the system to switch between different computation strategies. The multiplier can operate in modes that optimize for either speed or accuracy based on the specific application requirements, enabling flexible trade-offs between processing speed and computational precision.
3Adaptability or versatility
If traditional Booth multiplier architecture is implemented, then multiplication capability is achieved, but hardware complexity and chip area increase
Solution Approach 1:
The patent merges the Booth encoding logic with the existing memory array structure, utilizing the memory cells to store and process partial products. This integration eliminates the need for separate complex Booth multiplier hardware, reducing chip area and hardware complexity while maintaining full multiplication capability.
Solution Approach 2:
The patent makes the memory array multi-functional by using it not only for data storage but also for performing multiplication operations. The same memory cells that store input data are also used to hold partial products and accumulate results, eliminating the need for dedicated multiplier hardware and achieving universal resource utilization.
4Reliability
If multiple stages are used for partial sum generation, then complete multiplication is achieved, but latency increases
Solution Approach 1:
The patent performs preliminary generation and storage of partial products in memory cells during the first clock cycle. This preliminary action allows the final accumulation stage to proceed independently and in parallel with subsequent operations, significantly reducing the overall latency while ensuring complete multiplication is achieved.
Solution Approach 2:
The patent maintains continuity of useful action by overlapping the generation of partial products with their accumulation. Instead of waiting for all partial products to be fully generated before starting accumulation, the system continuously processes available data, keeping the computation pipeline full and reducing idle time between stages.
Data Source
AI summary
A compute-in-memory device may include a Booth encoder configured to receive at least one input of first bits, a Booth decoder configured to receive at least one weight of second bits and to output a plurality of partial products of the at least one input and the at least one weight, an adder configured to add a first partial product of the plurality of the partial products and a second partial product of the plurality of partial products before the Booth decoder generates a third partial product of the plurality of the partial products and to generate a plurality of sums of partial products, and a carry-lookahead adder configured to add the plurality of sums of partial products and to generate a final sum.