Shared Memory Composite Assignment Without Lock Contention
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Solution Overview
Problem
Existing parallel computing systems face challenges in ensuring well-defined, deterministic results when multiple processors access shared memory cells concurrently, often requiring locks to avoid conflicts and ensuring consistent execution order.
Innovation Solution
A shared memory architecture that allows multiple processors to perform concurrent composite assignments, such as OR= and AND= operations on a shared memory cell without locks, by integrating a feedback loop within the memory cell, ensuring the new result does not replace the previous data, thus allowing processors to read and write concurrently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional lock-based synchronization mechanisms are used to ensure thread-safe memory access, then data consistency and reliability are improved, but system performance and productivity deteriorate due to lock contention and overhead
Solution Approach 1:
The patent extracts the locking mechanism entirely from the memory access path by using lock-free data structures with atomic operations. Instead of acquiring locks before accessing shared memory, the invention uses compare-and-swap (CAS) atomic instructions to achieve thread-safe compound operations without blocking other threads, thereby eliminating lock contention while maintaining data consistency
Solution Approach 2:
The patent introduces atomic memory operations (CAS instructions) as an intermediary mechanism between threads and shared memory. These atomic operations provide a mediator that ensures thread-safe compound operations without requiring traditional locks, allowing concurrent access while maintaining memory consistency through hardware-supported atomicity
2Productivity
If lock-free data structures are used to improve system performance by eliminating lock contention, then productivity is improved, but implementation complexity and device complexity increase
Solution Approach 1:
The patent replaces the mechanical lock-based synchronization system with a substitution based on atomic hardware instructions. Instead of using software locks that require complex acquisition, release, and contention handling logic, the invention uses simple atomic compare-and-swap instructions provided by modern processors, significantly reducing implementation complexity while maintaining lock-free performance benefits
Solution Approach 2:
The patent changes the fundamental parameter of synchronization from software-managed locks to hardware-supported atomic operations. By leveraging CPU-level atomic instructions with well-defined memory ordering semantics, the invention simplifies the complexity of implementing thread-safe compound operations while achieving lock-free performance
3Reliability
If atomic operations are used to implement thread-safe compound operations, then reliability is improved through proper memory synchronization, but the number of operations required increases compared to locked operations
Solution Approach 1:
The patent applies preliminary action by using atomic compare-and-swap operations that atomically compare the current memory value with an expected value and perform updates only if the comparison succeeds. This preliminary comparison built into the atomic operation itself eliminates the need for separate read-modify-write sequences, reducing the total number of operations required while ensuring proper memory synchronization
Data Source
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AI summary
It is an object of the disclosed technique to provide a novel method and system for shared concurrent access to a memory cell. In accordance with the disclosed technique, there is thus provided a system for shared concurrent access to a memory cell, which includes at least one shared memory cell, an evaluator and a plurality of processing agents coupled to the input of the evaluator. The evaluator is further coupled with the at least one memory cell. The evaluator is configured to evaluate an expression for performing multiple concurrent composite assignments on the at least one shared memory cell. The evaluator further allows each of the plurality of processing agents to perform concurrent composite assignments on the at least one shared memory cell. The composite assignments do not include a read operation of the at least one shared memory cell by the plurality of processing agents.