Receiver Buffer Circuit With Duty Skew Compensation

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Solution Overview

Problem

Semiconductor receiver circuits face challenges in maintaining stable output characteristics due to variations in heterogeneous power supply voltages, which affect data reception and processing.

Innovation Solution

Incorporating a buffer circuit configuration with first and second logic gates coupled to internal and external voltage terminals, enabling compensation for duty skew in buffer signals based on external voltage levels, and utilizing enable signals to manage data reception operations across different modes (low-speed and high-speed) to stabilize output.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the receiver circuit operates with heterogeneous power supply voltages (external and internal), then the circuit can support both low-speed and high-speed modes, but the output characteristics become unstable due to voltage variations

Engineering Contradiction:

Improvesupport for multiple operating modesVSAvoidoutput characteristic stability

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies parameter changes by dynamically adjusting the duty cycle of buffer signals based on the detected external voltage level. When the external voltage indicates high-speed mode operation, the circuit compensates for duty skew by modifying the buffer signal characteristics, thereby maintaining stable output characteristics across different power supply conditions while supporting both low-speed and high-speed modes

Inventive Principle:

Principle #35Parameter changes

2Reliability

If the circuit compensates for duty skew based on external voltage level, then output stability is improved, but the circuit complexity increases due to additional control mechanisms

Engineering Contradiction:

Improveoutput characteristic stabilityVSAvoidbuffer circuit structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements feedback by detecting the external voltage level and using this information to control the duty cycle compensation of buffer signals. The circuit monitors the power supply condition and automatically adjusts the buffer operation accordingly, achieving stable output characteristics through a controlled feedback mechanism rather than complex hardwired logic

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent achieves multi-functionality by designing the buffer circuit to operate in both low-speed and high-speed modes using the same basic structure. The dual-mode operation is enabled through voltage-level detection and conditional control signals, allowing a single circuit to perform multiple functions without requiring separate dedicated circuits for each mode

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11799481B2Buffer circuit, receiver circuit including the buffer circuit, and semiconductor apparatus including the receiver circuit

Publication Date: 2023.10.24 SK HYNIX INC

AI summary

The present technology may include: a first logic gate coupled to an internal voltage terminal and configured to receive data and invert and output the data according to a first enable signal; and a second logic gate coupled to the internal voltage terminal and configured to invert an output of the first logic gate and to output an inverted output as a first buffer signal according to the first enable signal, and configured to compensate for a duty skew of the first buffer signal according to a level of an external voltage.