Phased-Clock Transmitter Circuit for Faster Serial Slew Rate

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Solution Overview

Problem

Transmitter circuits face reduced performance due to skew occurring between multiple clock signals, which affects the serializer's ability to generate a serial signal effectively.

Innovation Solution

A transmitter circuit design that utilizes a multiplexer with multiple selection circuits driven by clock signals of different phases to increase the slew rate of the serial signal, achieved by simultaneously driving two or more selection circuits to reduce output capacitance and enhance performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple clock signals are used to drive the serializer, then the serial signal generation capability is improved, but clock skew occurs between the signals

Engineering Contradiction:

Improveserial signal generation capabilityVSAvoidclock signal timing accuracy

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The patent divides the single clock signal into multiple phase-separated clock signals (e.g., four phases at 90-degree intervals) to drive multiple selection circuits simultaneously. This segmentation allows parallel processing of multiple data lines while maintaining synchronized operation through the phased clock structure.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent combines multiple selection circuits operating in parallel to collectively drive a single output node. By merging the output capabilities of multiple circuits, the system achieves higher slew rate and improved serial signal generation while the phased clock synchronization mitigates skew effects.

Inventive Principle:

Principle #5Merging (Combining)

2Speed

If two or more selection circuits simultaneously drive the output node, then the slew rate of the serial signal is increased, but the circuit complexity increases

Engineering Contradiction:

Improveslew rate of serial signalVSAvoidnumber of selection circuits

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

Each selection circuit is designed to perform multiple functions: selecting data from different parallel lines, synchronizing with phased clock signals, and contributing to the collective output drive. This multi-functionality reduces the need for separate dedicated components for each function.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent changes the operational parameters of the selection circuits by applying phased clock signals with specific phase differences (e.g., 90 degrees). This parameter change enables the circuits to operate in a coordinated manner, achieving high slew rate without requiring excessive complexity in the individual circuit designs.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentEP4106203B1Transmitter circuit and method of operating same

Publication Date: 2026.02.25 SAMSUNG ELECTRONICS CO LTD

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AI summary

A transmitter circuit (1) that receives parallel signals (D(1:4)) and outputs a serial signal (D_Tx) in response to the parallel signals may include; a clock generator (20) generating first clock signals (CK(1:4)) having different respective phases, a multiplexer (10) including selection circuits (11, 12, 13, 14) respectively configured to selectively provide at least two of the parallel signals (D1, D2 or D2, d3 or D3, D4 or D4, D1) to an output node in response to at least two of the first clock signals (Ck1, Ck2 or Ck2, Ck3 or Ck3, Ck4 or Ck4, Ck1), and an output driver (15) generating the serial signal (D_Tx) by amplifying a signal at the output node.