Interrupt Controller Clock Gating for Low-Power Signal Capture
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Solution Overview
Problem
Conventional interrupt controllers face challenges in managing interrupt signals, particularly safety fault signals, without increasing microcontroller consumption when transitioning to low power modes, risking missed signals.
Innovation Solution
An interrupt controller with a control circuit that automatically generates a controller clock signal from an external clock signal upon receipt of an interrupt signal, ensuring timely delivery of output interrupt signals while minimizing power consumption by gating the clock signal as necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the interrupt controller operates continuously with a clock signal, then all interrupt signals are processed without omission, but power consumption increases
Solution Approach 1:
The interrupt controller dynamically changes its operational state based on interrupt signal presence. When an interrupt signal is detected, the controller transitions to an active state where it processes the signal with full clock signaling. When no interrupt signals are present, the controller transitions to a low-power state with reduced or gated clock signaling, thus adapting its behavior to current needs and reducing unnecessary power consumption.
Solution Approach 2:
Instead of continuous operation, the interrupt controller uses periodic sampling or event-triggered activation. The controller activates clock signaling periodically or only when interrupt signals are detected, rather than maintaining continuous clock operation. This periodic action pattern allows the system to maintain reliability during critical moments while significantly reducing average power consumption during idle periods.
2Use of energy by moving object
If the interrupt controller operates in low power mode with gated clock signal, then power consumption is reduced, but interrupt signals may be missed
Solution Approach 1:
The system performs preliminary detection of interrupt signals before fully activating the interrupt controller. External interrupt inputs are monitored even in low-power mode, and when an interrupt signal is detected, the controller is awakened or activated in advance to process the signal properly. This preliminary action ensures that no interrupt signals are missed while minimizing the duration of high-power operation.
Solution Approach 2:
An intermediary mechanism or circuit is introduced between the low-power state and full operation. This intermediary layer monitors for interrupt signals and conditions the activation of the interrupt controller, ensuring smooth transitions between power states. The intermediary ensures that interrupt signals are not lost during state transitions and that the controller is activated at the appropriate moment to handle interrupts reliably.
3Loss of energy
If the controller clock signal is gated to reduce power consumption, then energy efficiency improves, but the timing of interrupt signal delivery may be affected
Solution Approach 1:
The system changes the clock signal parameters (frequency, duty cycle, or presence) based on operational requirements. During interrupt processing, the clock signal is provided at full strength and appropriate frequency to ensure timely delivery. During idle periods, the clock signal parameters are adjusted or gated to reduce energy consumption. This dynamic parameter adjustment allows the system to optimize the trade-off between energy loss and time loss adaptively.
Data Source
AI summary
In accordance with an embodiment, an electronic device includes: an interrupt controller having an input for receiving a controller clock signal, and an output, the interrupt controller configured to deliver an output interrupt signal on the output when the controller clock signal is active, and a control circuit comprising, an input interface for receiving at least one interrupt signal likely to emanate from at least one item of equipment external to the device, a clock input for receiving an external clock signal, and a first controller connected to the input interface and to the clock input, the first controller configured to automatically generate the controller clock signal from the external clock signal from when the at least one interrupt signal is asserted until a delivery of a corresponding output interrupt signal.