Shared XOR-XNOR Comparator Circuit for Faster DRAM Error Checking
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Solution Overview
Problem
As semiconductor memory technologies advance and memory density increases, errors in Dynamic Random Access Memory (DRAM) storage become more prevalent, necessitating effective error detection and correction techniques, but existing solutions are inefficient in terms of circuit area and operation speed.
Innovation Solution
A comparison system is developed that integrates a common module with both XOR and XNOR logical units, sharing a circuit area to reduce overall space while allowing for larger areas for each unit, thereby enhancing their driving capability and operation speed, facilitating improved error detection and correction in memory systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If separate circuits are used for XOR and XNOR operations, then each unit can be optimized independently, but the total circuit area increases
Solution Approach 1:
The patent combines the XOR and XNOR circuits into a single integrated comparison circuit that shares common modules (such as the common source terminal circuit and control logic). This merging reduces the total circuit area while maintaining the functional independence needed for both operations to proceed in parallel, thus resolving the contradiction between area reduction and speed maintenance.
Solution Approach 2:
The comparison circuit is designed with universal modules that can serve both XOR and XNOR operations. The common module receives control signals and data inputs that are routed to both logical units, allowing the same hardware resources to be utilized for multiple functions simultaneously, thereby reducing overall circuit area without sacrificing operational capability.
2Speed
If larger area is allocated to XOR and XNOR units, then driving capability and operation speed improve, but total circuit area increases
Solution Approach 1:
By merging the XOR and XNOR circuits into a shared architecture with common modules, the patent enables each logical unit to have adequate area allocation for high-speed operation while avoiding redundant circuitry. The shared control logic and input routing reduce overall area while maintaining sufficient resources for fast operation in both units.
Solution Approach 2:
The circuit employs dynamic control signals that can selectively activate or configure the XOR and XNOR paths based on operational requirements. This dynamic configuration allows the circuit to optimize resource allocation in real-time, ensuring that each logical unit receives adequate driving capability when needed while minimizing total area through shared resources during simultaneous operation.
Data Source
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AI summary
Embodiments of the disclosure provide a comparison system including at least one comparison circuit, the comparison circuit including: a common module, connected to a power supply signal and a ground signal, and configured to control output of the power supply signal or the ground signal based on a first signal and a second signal which are inverted; a first logical unit, connected to the common module, and configured to receive a third signal and a fourth signal which are inverted, and output a first operation signal which is an exclusive OR (XOR) of the first signal and the third signal; and a second logical unit, connected to the common module, and configured to receive the third signal and the fourth signal, and output a second operation signal which is a not exclusive OR (XNOR) of the first signal and the third signal. The embodiments of the disclosure facilitate an operation speed of the comparison system to be improved.