RF-Sampling Digital Power Amplifier With Wide LC Tuning Range
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Solution Overview
Problem
Switching power amplifiers for ultra-wideband (UWB) transmitters face challenges in combining amplitude code and clock signals at RF frequency without timing violations and achieving a wide tuning range while maintaining efficiency and linearity, particularly due to difficulties in tuning series LC networks and capacitive division.
Innovation Solution
The design incorporates a switching power amplifier with logic circuitry generating differential signals based on received and delayed amplitude codes, and a differential-to-single ended conversion circuit using an LC tuning circuit with a variable capacitor, allowing for relaxed timing requirements and improved tuning range by breaking the center-tap connection of the primary coil and adding a series variable capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a series LC network is used for tuning in a switching power amplifier, then the amplifier can achieve saturated power operation with high efficiency, but the tuning range is limited and timing violations occur when combining amplitude code and clock signals at RF frequency
Solution Approach 1:
The primary coil is divided into two separate coils (first coil and second coil) that are coupled in series. This segmentation allows independent tuning of each coil's inductance through separate switches, enabling a wider overall tuning range while maintaining the series LC network's efficiency benefits
Solution Approach 2:
Switches are introduced to dynamically control the connection of capacitor units in series or parallel configurations. This dynamic reconfiguration allows the total capacitance to be adjusted across a wide range, achieving wide tuning range while maintaining saturated power operation and high efficiency
2Extent of automation
If amplitude code and clock signals are combined at RF frequency in a switching power amplifier, then digital power amplification can be achieved, but timing violations occur that degrade performance
Solution Approach 1:
The clock signal is delayed by a controlled amount before being combined with the amplitude code signals. This preliminary delay action ensures that the signals are properly synchronized and prevents timing violations, enabling reliable digital power amplification
Solution Approach 2:
A delay circuit is introduced as an intermediary element between the clock signal source and the signal combination point. This intermediary component adjusts the timing relationship between signals, preventing timing violations while maintaining digital power amplification functionality
3Device complexity
If capacitive division is used in the LC tuning circuit, then the circuit can be simplified, but the tuning range and efficiency are degraded
Solution Approach 1:
The capacitor network is segmented into multiple switchable capacitor units that can be independently controlled. This segmentation replaces the limiting capacitive division approach with a flexible switched-capacitor configuration, achieving wide tuning range without degrading efficiency
Solution Approach 2:
The circuit transitions from fixed capacitive division to dynamically changeable capacitance values through switch control. By changing the effective capacitance parameters through switching different capacitor units in or out of the circuit, wide tuning range is achieved while maintaining simplicity and efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient operation of switching power amplifiers in UWB transmitters by relaxing timing requirements, enhancing tuning range, and maintaining high efficiency and linearity, thus addressing the challenges of combining amplitude and clock signals and achieving desired output power.
Implementation Method 1
a differential-to-single ended conversion circuit using an LC tuning circuit with a variable capacitor, allowing for relaxed timing requirements and improved tuning range
Data Source
AI summary
A switching power amplifier includes logic circuitry that generates first and second components of a differential signal, based on received amplitude code and a delayed version of the same. The amplitude code includes a sign and a magnitude. When the sign is positive, a first logic path is configured to generate the first component based on the received amplitude code and the second logic path is configured to generate the second component based on the delayed amplitude code. When the sign is negative, the first logic path is configured to generate the first component based on the delayed amplitude code and the second logic path is configured to generate the second component based on the received amplitude code. The switching power amplifier further includes a differential-to-single ended conversion circuit configured to generate a single-ended signal based on the differential signal.