Memory Bit Cell Selection Layout for Low-Power Programming
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Solution Overview
Problem
Programming of memory bit cells in non-volatile memory devices consumes significant power due to the unnecessary activation of entire rows and columns within the memory array.
Innovation Solution
Incorporation of a logic gate into each memory bit cell and the use of second word lines oriented substantially perpendicular to bit lines, allowing for individual selection and programming of memory bit cells without activating entire rows or columns, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional row and column activation method is used for programming memory bit cells, then the programming operation can be performed, but the power consumption increases significantly due to unnecessary activation of entire rows and columns
Solution Approach 1:
The patent divides the memory array into smaller programmable units by introducing bit selection lines that can independently activate individual bit cells within a row or column. This segmentation allows only the specific bit cell requiring programming to be activated, rather than activating the entire row or column, thereby reducing power consumption while maintaining the ability to perform programming operations.
2Loss of energy
If individual bit cell selection is implemented, then power consumption is reduced, but the device complexity increases due to additional bit selection lines and logic gates
Solution Approach 1:
The patent merges the functionality of row selection, column selection, and bit selection into a unified addressing scheme. The bit selection lines are integrated with the existing row and column selection mechanisms, allowing the system to selectively activate only the necessary bit cells while using the same control logic infrastructure. This merging approach reduces the need for completely separate control circuits, thereby limiting the increase in device complexity.
Data Source
AI summary
Systems, devices, and methods are described herein for a programmable memory array. A programmable memory system includes an array of programmable memory bit cells. A memory bit cell of the array includes a first transistor of a first type controlled by a bit line, a second transistor of a second type responsive to a first word line and a second word line via a logic gate, and a third transistor of the second type responsive to the word line. The first word line is positioned substantially perpendicular to the bit line, and the second word line is positioned substantially parallel to the bit line. The first word line is activated via an X portion of an address. While the second word line is activated via a Y portion of the address.