CIM Bit Cell Layout With RWL Initialization for Uniform MAC Operation
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Solution Overview
Problem
Compute-in-memory (CIM) arrays used in neural networks for machine learning applications occupy a large area of integrated circuits and have performance variations due to non-uniform operation of CIM bit cell circuits, affecting reliability and efficiency.
Innovation Solution
The implementation of CIM bit cell circuits with a read word line (RWL) circuit in a specific orientation within a CIM bit cell array layout, including memory bit cell circuits, true and complement pass-gate circuits, and RWL transistors, which are coupled to a ground voltage rail for initializing product data, and a plurality of gates extending in one direction and separated in another, enhancing uniformity and operation reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CIM bit cell circuits are implemented in conventional layouts without RWL circuits, then the area occupation is reduced, but the operation uniformity and reliability deteriorate
Solution Approach 1:
The RWL circuit is merged with the bit cell circuit structure by integrating the RWL transistor within the bit cell layout. The RWL transistor shares the same diffusion region and gate structure as the storage transistors, combining the initialization function with the storage function in a unified compact structure. This merging allows the RWL circuit to be incorporated without significantly increasing the overall area while ensuring uniform operation across all bit cells.
Solution Approach 2:
The RWL transistor is designed to serve multiple functions: it acts as both an initialization device for resetting the product node and as part of the read operation control. The same RWL transistor and associated circuitry are used for both initializing the bit cell before computation and for reading the results, providing multi-functionality that reduces the need for separate dedicated circuits and maintains area efficiency.
2Reliability
If CIM bit cell circuits use standardized orientations with RWL circuits, then the operation uniformity improves, but the device complexity increases
Solution Approach 1:
The RWL circuit is implemented with local customization within each bit cell orientation. Each bit cell contains an RWL transistor positioned and configured according to its specific orientation (e.g., north, south, east, west), with the gate connected to the RWL line and the source/drain terminals positioned to match the orientation. This local quality approach ensures uniform operation across all orientations while avoiding the need for a completely standardized complex circuit design for every cell.
Solution Approach 2:
The RWL transistor is designed with asymmetric positioning and connection depending on the bit cell orientation. For example, in north-oriented bit cells, the RWL transistor may be positioned with its gate extending in one direction, while in south-oriented bit cells, the same transistor is positioned and connected in the opposite direction. This asymmetric design allows the circuit to adapt to different orientations while maintaining uniform operational characteristics across the entire array.
3Measurement precision
If CIM arrays implement multiply-accumulate operations with proper initialization, then the calculation accuracy improves, but the loss of time increases
Solution Approach 1:
The RWL circuit performs preliminary initialization of the product node before the multiply-accumulate operation begins. By resetting the product node to a known state (typically zero or ground potential) in advance, the circuit ensures that subsequent calculations start from a clean state, improving calculation accuracy. This preliminary action is integrated into the operational sequence without requiring separate dedicated initialization cycles.
Solution Approach 2:
The RWL initialization operation is seamlessly integrated into the continuous operational flow of the CIM array. The initialization occurs in parallel with other operations or is immediately followed by the computation without idle transitions. The RWL line can continuously initialize multiple bit cells in sequence, maintaining continuous useful action rather than introducing idle time between operations.
Data Source
AI summary
Compute-in-memory (CIM) bit cell array circuits include CIM bit cell circuits for multiply-accumulate operations. The CIM bit cell circuits include a memory bit cell circuit for storing a weight data in true and complement form. The CIM bit cell circuits include a true pass-gate circuit and a complement pass-gate circuit for generating a binary product of the weight data and an activation input on a product node. An RWL circuit couples the product node to a ground voltage for initialization. The CIM bit cell circuits also include a plurality of consecutive gates each coupled to at least one of the memory bit cell circuit, the true pass-gate circuit, the complement pass-gate circuit, and the RWL circuit. Each of the CIM bit cell circuits in the CIM bit cell array circuit is disposed in an orientation of a CIM bit cell circuit layout including the RWL circuit.