Memory Power Segmentation for Higher-Voltage DVS Scans
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Solution Overview
Problem
Existing memory designs limit the power supply voltage increase during dynamic voltage stress (DVS) scans, leading to inadequate fault unmasking and costly returns due to temperature spikes and reduced scan effectiveness.
Innovation Solution
A memory configuration with a power management circuit that powers down the bitcell array while maintaining power to the memory periphery during a DVS scan, allowing for a higher and more sustained power supply voltage to uncover faults without damaging the memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power supply voltage is increased during DVS scan to unmask faults, then fault detection capability is improved, but temperature spikes occur causing damage to the memory
Solution Approach 1:
The memory system is segmented into bitcell array and memory periphery components with separate power control. The power management circuit independently controls power delivery to each segment, allowing the bitcell array to be powered down while maintaining power to the memory periphery during DVS scans, thereby enabling high voltage stress testing without causing temperature spikes that would damage the entire memory system
Solution Approach 2:
The power management circuit is configured to automatically power down the bitcell array before applying high voltage stress during DVS scans. This preliminary action of removing vulnerable components from the powered state prevents temperature spikes from occurring in the first place, allowing safe fault unmasking in the remaining memory periphery
2Reliability
If power supply voltage is increased during DVS scan, then fault unmasking is improved, but the power supply voltage increase that could be applied is limited
Solution Approach 1:
By segmenting the memory into independently controllable power domains (bitcell array and memory periphery), the system can apply high voltage stress to the memory periphery without subjecting the bitcell array to the same stress. This segmentation removes the limiting factor that previously constrained the maximum voltage increase to levels that would cause temperature spikes in the bitcell array
Solution Approach 2:
The power management circuit provides localized power control, creating different power states in different parts of the memory system simultaneously. The bitcell array is in a powered-down state while the memory periphery remains powered, allowing each region to have optimal power conditions for its specific function during DVS scanning
3Reliability
If bitcell array is powered on during sleep mode without retention, then memory functionality is maintained, but power consumption increases and leakage current is generated
Solution Approach 1:
The power management circuit dynamically adjusts the power state of the bitcell array based on operational requirements. During sleep mode without retention, the bitcell array is transitioned to a powered-down state to eliminate leakage current and reduce power consumption, while the memory periphery remains powered to maintain basic functionality. This dynamic power management allows the system to adapt its power consumption to the actual operational needs
Data Source
AI summary
A memory is provided that is configured to practice a sleep mode without retention in which a both bitcell array and a memory periphery are powered down responsive to an assertion of sleep mode without retention control signal. The sleep mode without retention control signal is also asserted during a DVS scan to power down the bitcell array. The memory includes a power management circuit that responds to an assertion of a DVS scan control signal to prevent the assertion of the sleep mode without retention control signal from causing a power down of the memory periphery during the DVS scan. The memory periphery may thus be thoroughly tested by the DVS scan because leakage current from the bitcell array is prevented by the powering down of the bitcell array.