Fixed Binary Adder Layout for Faster Addition in Small Area
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Solution Overview
Problem
Conventional addition circuits are slow due to sequential processing, and there is a need for a fixed binary adder that can efficiently perform operations like normalization and round processing with reduced circuit area and power consumption.
Innovation Solution
A fixed binary adder design incorporating multiple transfer logic stages and a summation logic stage using logic gates such as AND, OR, and buffer gates to process an N-bit second operand with an N-bit fixed value, generating N+1-bit output data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional sequential addition circuits are used, then circuit structure is simple, but addition speed is slow
Solution Approach 1:
The addition operation is segmented into multiple stages (first addition stage, second addition stage, third addition stage) that process different bit positions in parallel. Each stage handles specific carry propagation paths, allowing simultaneous computation rather than sequential processing, thereby increasing addition speed while maintaining manageable circuit complexity through modular organization.
2Area of stationary object
If fixed binary adder with N-bit operand is used, then circuit area is reduced, but output precision may be limited
Solution Approach 1:
The circuit extends the output from N bits to N+1 bits by adding an additional output terminal that handles the final carry-out. This dimensional extension in the output space allows the fixed binary adder to maintain N-bit input efficiency while achieving (N+1)-bit precision output, effectively resolving the precision limitation without significantly increasing circuit area.
Data Source
AI summary
A fixed binary adder adds an “N”-bit second operand to a first operand having an “N”-bit fixed value (N=2M, M is a natural number) to generate “N+1”-bit output data. The fixed binary adder includes a plurality of transfer logic stages each configured with at least one logic gate, and a summation addition logic configured to generate the “N+1”-bit output data by using the “N”-bit second operand and transfer data that is generated through the plurality of transfer logic stages. The logic gate is configured with one of an AND gate, an OR gate, and a buffer gate.