Digital Delay Lock Loop Phase Detection to Prevent Latency Jumps
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Solution Overview
Problem
Conventional delay lock loop circuits experience phase detection errors due to layout mismatch and component asymmetry, leading to instability and frequent latency jumps and unlocked events, which degrade their performance.
Innovation Solution
A delay lock loop circuit that includes a receiver, a delay line circuit, a clock signal generator, and a phase detecting circuit, where the phase detecting circuit samples the reference clock signal with a feedback clock signal to generate a detection result and adjusts the delay indication signal to effectively lock the phase, thereby avoiding latency jumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an analogy amplifier is used to detect phase difference, then the delay lock loop circuit can detect phase difference between clock signals, but phase detection errors occur due to layout mismatch and component asymmetry leading to instability and latency jumps
Solution Approach 1:
The patent replaces the analog amplifier-based phase detection system with a digital phase detecting circuit. The digital circuit uses flip-flops and logic gates to detect phase differences by sampling the feedback clock signal against the reference clock signal, eliminating the sensitivity issues of analog components like amplifiers that suffer from layout mismatch and component asymmetry.
Solution Approach 2:
The patent uses digital sampling to create a copy of the reference clock signal at specific phases, comparing it with the feedback clock signal. This digital copying approach allows precise phase detection without the sensitivity problems of analog amplification, where small variations in component characteristics cause large errors.
2Measurement precision
If the amplifier sensitivity is increased to improve phase detection, then detection precision improves, but latency jump and unlocked events happen more frequently
Solution Approach 1:
The patent replaces the high-sensitivity analog amplifier with a digital sampling system that achieves phase detection without amplification. The digital circuit uses clean, stable clock signals and logic operations to detect phase differences, avoiding the instability that occurs when analog amplifiers are pushed to high sensitivity levels.
Solution Approach 2:
The patent employs periodic sampling of the clock signals at specific phases using flip-flops triggered by the reference clock signal. This periodic digital sampling provides stable, repeatable phase detection points without the continuous instability associated with high-gain analog amplification.
3Device complexity
If conventional phase detection methods are used, then the circuit structure remains simple, but performance is reduced due to frequent latency jumps and unlocked events
Solution Approach 1:
The patent replaces the simple but flawed analog amplifier circuit with a digital phase detection circuit using flip-flops and logic gates. While the digital circuit has more components, it provides superior performance by eliminating latency jumps and unlocked events, achieving better overall productivity and reliability.
Solution Approach 2:
The digital phase detecting circuit generates its own clean, stable timing signals from the reference clock signal, making it self-sufficient and immune to the external noise and instability that plague analog amplifier-based systems. The circuit serves itself with stable timing without requiring external stabilization.
Data Source
AI summary
A delay lock loop circuit includes a receiver, a delay line circuit, a clock signal generator and a phase detecting circuit. The receiver receives a clock signal and a reference voltage and generates a reference clock signal according to the clock signal and the reference voltage. The delay line circuit is coupled to the receiver and generates a delayed clock signal by delaying the reference clock signal with a delay indication signal. The clock signal generator generates an output clock signal according to the delayed clock signal. The phase detecting circuit generates a detection result by sampling the reference clock signal with a feedback clock signal generated by the output clock signal, and generates the delay indication signal according to a digital value of the detection result.