DDR5 Refresh Control Circuit for Row Hammer Supplementary Refresh
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Solution Overview
Problem
Frequent switching of refresh modes in DDR5 SDRAM leads to vulnerabilities in row hammer protection, necessitating a robust control strategy to prevent bit flipping in adjacent rows.
Innovation Solution
A refresh control circuit that includes a count flag circuit, count processing circuit, and first control circuit to generate a supplementary refresh indication signal when the refresh count reaches a preset range, ensuring row hammer protection across varying refresh modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If frequent switching of refresh modes is performed to adapt to different memory access patterns, then adaptability is improved, but row hammer protection reliability deteriorates
Solution Approach 1:
The patent performs preliminary actions by counting refresh operations in advance and proactively issuing supplementary refresh commands before bit flipping can occur. The count circuit monitors refresh operations and triggers protective refresh commands when thresholds are reached, preventing row hammer attacks rather than reacting after damage occurs.
Solution Approach 2:
The patent implements feedback mechanisms where the count circuit continuously monitors the number of refresh operations, and this count information feeds back to the control logic to determine when supplementary refresh commands should be issued. This closed-loop feedback ensures row hammer protection adapts to actual refresh activity patterns.
2Reliability
If supplementary refresh operations are performed frequently to enhance row hammer protection, then reliability is improved, but energy consumption increases
Solution Approach 1:
The patent changes the parameter of refresh operation frequency dynamically based on counted refresh activity. Instead of performing supplementary refresh operations at a fixed high frequency, the system adjusts the timing and frequency of supplementary refresh commands based on the actual count of refresh operations, optimizing energy consumption while maintaining protection.
Solution Approach 2:
The patent applies partial action by issuing supplementary refresh commands only when the count of refresh operations reaches predetermined thresholds. Rather than continuously performing supplementary refresh operations, the system intervenes selectively at critical moments, reducing unnecessary energy consumption while maintaining adequate protection.
3Ease of operation
If the same-bank refresh command is masked in normal refresh mode to maintain mode consistency, then operational simplicity is improved, but functionality deteriorates
Solution Approach 1:
The patent makes the masking behavior dynamic rather than static. The same-bank refresh command masking is not fixed to a particular refresh mode but is dynamically controlled based on the current refresh operation count and system state. This allows the system to enable or disable same-bank refresh commands adaptively, combining operational simplicity with enhanced functionality.
Data Source
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AI summary
The present disclosure relates to the field of semiconductor circuit design, and in particular to a refresh control circuit and a memory. The refresh control circuit includes: a count flag circuit configured to generate and output a count flag signal at an active level based on a refresh activation signal when an all-bank refresh flag signal and a same-bank refresh flag signal are active; a count processing circuit configured to receive the count flag signal and count based on the count flag signal to generate a counting result; and a first control circuit configured to receive the counting result and generate and output, when the counting result is within a first preset range, a supplementary refresh indication signal at an active level. The supplementary refresh indication signal, when active, indicates that an associated memory performs a supplementary refresh operation.