Scalable MUTEX Arbiter for Non-Persistent Signal Requests
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional arbiters are limited in scalability and unsuitable for processing non-persistent signals, such as those generated by analog circuits, due to issues like glitches and jitters, and require custom gates not available in common libraries, limiting their ability to handle a large number of requests efficiently.
Innovation Solution
A scalable arbiter architecture using asynchronous circuits and MUTEX logic circuits that sanitize non-persistent signals, allowing for efficient arbitration of an arbitrary number of requests while maintaining low latency and area efficiency, utilizing common gate libraries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional arbiters are used to process non-persistent signals, then the arbitration function is provided, but the arbiter cannot effectively handle glitches and jitters, leading to unreliable arbitration results
Solution Approach 1:
The patent applies preliminary action by sanitizing non-persistent signals before they enter the arbitration logic. Asynchronous circuit elements clean up glitches and jitters in advance, ensuring that only valid request signals are processed by the arbiter, thus preventing harmful factors from affecting arbitration reliability
Solution Approach 2:
The patent introduces asynchronous circuit elements as intermediary components between the non-persistent signal sources and the arbitration logic. These intermediaries sanitize the signals by filtering out glitches and jitters, allowing the arbiter to process only clean, valid requests, thereby resolving the contradiction between handling non-persistent signals and maintaining reliability
2Adaptability or versatility
If custom gates are used in arbiter design, then the arbitration functionality is achieved, but the device complexity increases and common gate libraries cannot be used
Solution Approach 1:
The patent achieves universality by designing the arbiter using only standard logic gates (AND, OR, NOT, XOR) that are available in common gate libraries. The asynchronous circuit elements perform multiple functions including signal sanitization, request registration, and grant generation using only universal logic gate building blocks, eliminating the need for custom gates while maintaining full arbitration capability
Solution Approach 2:
The patent substitutes complex custom gate implementations with combinations of standard logic gates. Instead of using specialized custom gates for arbitration, the design uses conventional logic gates arranged in asynchronous circuit configurations, replacing the need for mechanical or specialized hardware components with standard digital logic elements
3Quantity of substance
If the arbiter processes a large number of concurrent requests, then the arbitration coverage is improved, but the latency and area increase
Solution Approach 1:
The patent applies segmentation by dividing the arbitration process into distinct asynchronous stages: request registration, arbitration evaluation, and grant output. Each stage is handled by separate logic circuit blocks that operate independently, allowing multiple requests to be processed through different segments simultaneously without increasing overall latency, thus enabling the arbiter to handle large numbers of concurrent requests efficiently
Solution Approach 2:
The patent uses dynamic asynchronous circuit elements that adapt their behavior based on the current state of requests. The arbitration logic dynamically responds to signal transitions and automatically progresses through arbitration stages without fixed timing constraints, allowing the system to maintain low latency regardless of the number of concurrent requests by adjusting the arbitration pace dynamically
4Quantity of substance
If the arbiter processes a large number of concurrent requests, then the arbitration coverage is improved, but the circuit area increases
Solution Approach 1:
The patent segments the arbitration logic into modular logic circuit blocks that can be efficiently laid out on the chip. Each block handles specific arbitration functions for subsets of requests, allowing compact arrangement and reducing overall circuit area while maintaining the capability to process large numbers of concurrent requests through parallel operation of segmented blocks
Data Source
AI summary
Systems and devices for signal arbitration are described. A plurality of asynchronous circuits can receive a plurality of non-persistent signals representing a plurality of requests and sanitize the plurality of non-persistent signals to generate a plurality of persistent signals. At least one logic circuit can arbitrate the plurality of persistent signals, where each one of the at least one logic circuit can include a mutual exclusive circuit configured to arbitrate two signals. Each logic circuit is one of a first logic circuit, a second logic circuit and a third logic circuit different from one another. A number of copies of the first logic circuit can be implemented in an initial level of arbitration and a number of copies of the second logic circuit and the third logic circuit can be implemented in additional levels of arbitration.