1T 2R Resistive Memory Cell Scaling Through Vertical Stacking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current four transistor-four resistor (4T 4R) memory cell configurations face limitations in scaling due to the physical constraints of their design, which affects the miniaturization of memory cells such as ReRAM, PCRAM, and MRAM.
Innovation Solution
A scaled one transistor two resistor (1T 2R) memory cell configuration is developed, where multiple memory cells are connected longitudinally with a common metal connection in the middle, utilizing a shared selection transistor to enable effective scaling and vertical stacking, with independent current paths and self-aligned contacts for increased density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If 4T 4R memory cell configuration is used, then reliability is improved, but area increases and scaling is limited
Solution Approach 1:
The patent merges two memory cells into a single shared structure by combining their bottom electrodes into a common contact. This consolidation reduces the total area required while maintaining the functional integrity of each memory cell, directly addressing the area penalty associated with traditional 4T 4R configurations.
Solution Approach 2:
The shared bottom electrode contact serves multiple functions: it acts as the bottom electrode for both memory cells simultaneously and provides a common electrical connection point. This multi-functionality allows the structure to maintain reliability requirements while reducing area through component sharing.
2Quantity of substance
If memory cell size is reduced for scaling, then density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from planar scaling to vertical stacking by forming memory cells in three dimensions. The shared bottom electrode contact enables this vertical arrangement where multiple memory cells stack above a single contact, achieving higher density without requiring proportionally smaller feature sizes that would demand extreme manufacturing precision.
Solution Approach 2:
The memory cell structure is segmented into distinct vertical layers with the shared bottom electrode contact forming the base layer. This segmentation allows each layer to be formed and controlled independently, reducing the cumulative precision requirements compared to scaling all dimensions proportionally in a planar configuration.
3Area of stationary object
If 1T 2R configuration is implemented, then area is reduced, but device complexity increases
Solution Approach 1:
The patent merges the bottom electrode structures of multiple memory cells into a single shared contact. This consolidation simplifies the overall device structure by reducing the number of separate components while maintaining the 1T 2R configuration's area benefits, counteracting the potential increase in complexity through intelligent sharing of common elements.
Data Source
AI summary
A semiconductor structure includes a selection transistor having a first drain-source terminal, a second drain-source terminal, at least one channel region between the first and second source-drain terminals, and a gate adjacent the at least one channel region. A first vertical contact structure is connected to the first drain-source terminal. A second vertical contact structure is connected to the second drain-source terminal. A first resistive memory cell has a lower electrode coupled to the second vertical contact structure and has an upper electrode. A third vertical contact structure is connected to the upper electrode of the first resistive memory cell. A second resistive memory cell has an upper electrode coupled to the second vertical contact structure and has a lower electrode. A fourth vertical contact structure is connected to the lower electrode of the second resistive memory cell.