Digital Storage TRIZ Cases

A loop circuit averages synthesized clock phases to correct multi-phase skew, improving semiconductor data reliability with frequency-based control.

Oxide semiconductor storage preserves reconfigurable logic connections after power-off while supporting faster changes and lower power use.

Earliest-phase clock selection and shielding reduce multi-clock interference in memory delay circuits, improving signal accuracy.

A double-buffered DIMM topology adds board-level buffers and training schemes to expand memory capacity while preserving signal integrity.

Operating-mode phase interpolation compensates data strobe delay shifts from temperature and voltage changes to prevent memory write errors.

Redundancy lines and sub-array replacement detect memory faults in neuromorphic hardware while preserving deep learning accuracy and lowering power use.

Symmetric pull-up and pull-down diodes turn memory current into voltage output, removing CSA read circuits to save area and improve noise tolerance.

A dedicated bank-to-bank bus moves data within memory on the shortest path, cutting transfer time, power use, and external bus dependence.

Tracking cells tune SRAM word line pulse widths by array distance, cutting active power and avoiding crow-bar issues.

A mixed bit-cell layout stores LSBs with multi-element structures and MSBs with single-element cells to raise density without full-array complexity.

Alternating PMOS- and NMOS-biased clock repeaters cancel PVT-induced duty errors, improving memory timing reliability.

A code-controlled impedance circuit lets one receiver stage handle noise removal, duty correction, and equalization with less size and power.

Previous-cycle chip select preprocessing helps DRAM decode non-target ODT commands correctly in the second cycle and raise success rate.

Parity-based CA pattern checking in memory hardware speeds command bus training, improves validation quality, and reduces hang risk.

A switched resistor termination lets PAM memory links terminate at a lower voltage, cutting power use while preserving signal integrity.

A symmetric memory cell stores binary BNN weights with direct readout, cutting power use and memory size for parallel inference.

Parallel inverter chains and reset control cut power use and transmission errors in high-speed memory I/O under low-power conditions.

Pre-updating the oscillator cycle count before the N-th pulse shortens write training time while preserving counting accuracy under voltage and temperature shifts.

Status data sent during read latency lets the memory controller trigger retraining only when needed, improving data-clock alignment reliability.

High-power write pulses and low-power read pulses let a Y-branch phase-change waveguide perform all 16 Boolean operations without optical-electrical conversion.

A dedicated bank-to-bank bus enables parallel memory transfers without external bus use, reducing processing time and power consumption.

A voltage-mode return-path offset suppresses idle-channel noise, improving current-based displacement and inductance sensing in haptic transducers.

An offset-adjusted reference voltage helps DRAM receivers filter noise in low-amplitude differential signals and avoid data misjudgment.

Cross-coupled inverters and limited read current let a ternary memory cell store three states with higher density and reliable reads.

Internal configuration commands move data between FPGA subregion Block RAMs, cutting routing demand and easing timing and compilation bottlenecks.

Internal sync signals and clock-cycle counting align multiple DAC outputs on one clock edge while avoiding sampling-clock jitter.

Bitline and wordline override recovers faulty configuration memory cells, cutting IC yield fallout without intercepting every cell output.

Selective refresh based on memory access history cuts latency and power use in variable word length memory banks for data-heavy computing.

Logic runs inside memory cells by tuning FET threshold voltage and resistive states, cutting CPU-memory data transfer latency and energy.

Direct analog transfer between resistor arrays removes interlayer ADCs, cutting chip area and power while speeding neural IC processing.

A double-buffered DIMM channel uses board-level buffers and timing control to expand memory capacity without sacrificing signal integrity or data rates.

Equalization and automatic CDR reset reduce ISI jitter and false lock during memory link speed switching, improving transfer reliability.

Fine-tuning circuits and a delay path enable sub-step clock phase advance and delay, improving phase alignment in high-speed semiconductor signals.

Background clock distortion calibration adjusts trim values when DCC conditions are met, preserving timing margins across voltage and temperature changes.

Internal parity checks return CA sampling feedback from the memory device, reducing firmware coordination and shortening command bus training.

Computing inside the memory array cuts data movement, raising parallel throughput while reducing energy use and processor cost.

A 3D ground grid uses orthogonal ground lines and vertical vias to cut return-path inductance and crosstalk in dense superconducting circuits.

A repeater module regenerates a recovery clock between host and spaced LPDDR memory to preserve in-vehicle signal quality.

Per-line read reference voltage training corrects duty errors from data-line swing deviations, improving signal integrity and valid window margin.

Averaging synthesized multi-phase clock signals corrects skew, improving memory data reliability while allowing lower-power operation at low frequencies.

A mode detection circuit switches between NRZ and PAM4 using channel conditions to improve memory link bandwidth while limiting loss.

Programmable trim circuitry corrects input-buffer voltage mismatch to cut leakage current and improve setup, hold, and data reliability.

Separate current control for the latch improves high-speed data sensing accuracy, cuts edge delays, and helps prevent memory receiver faults.

A symmetric output stage coordinates clock edges to reduce skew and duty errors in high-frequency memory clock conversion.

Internal MRAM or ReRAM configuration bits replace external FPGA memory to improve security, reduce circuitry, and shorten boot time.

Strategic placement of I/O blocks, power switches, decoupling capacitors, and PLL cuts DDR PHY clock latency, jitter, power, and area.

An impedance path and selectively coupled third inverter harden volatile storage against SEUs without slowing write time or adding much area.

Redundant inverters and parallel FETs detect data-line voltage drops without a reference circuit, improving NVM read accuracy under process and thermal variation.

Tracking cells adjust SRAM word-line pulse widths by row distance, cutting active power and avoiding crow-bar issues.

Threshold-based precharge and keeper control cut dynamic and leakage power while reducing false detections in dynamic nodes.