Multi-Phase Clock Phase Correction Using Averaging Loop Buffers

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Solution Overview

Problem

Semiconductor memory circuits face performance degradation due to phase skew in multi-phase clock signals, which affects data reliability.

Innovation Solution

A phase correction circuit that includes multiple signal paths and a loop circuit to correct phase skew by averaging signal phases, with programmable buffers and control codes adjusting drivability based on operation frequency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If phase correction loop is enabled to correct phase skew, then data reliability is improved, but power consumption increases

Engineering Contradiction:

Improvedata reliabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The phase correction loop is dynamically enabled or disabled based on operation frequency. At high frequencies where phase skew degrades reliability, the loop is enabled. At low frequencies where phase skew is negligible, the loop is disabled to save power. This dynamic configuration resolves the contradiction by adapting the power-consuming correction mechanism only when actually needed for reliability.

Inventive Principle:

Principle #15Dynamics

2Reliability

If programmable buffers are used to adjust drivability, then signal quality is improved, but device complexity increases

Engineering Contradiction:

Improvesignal qualityVSAvoiddevice complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

Programmable buffers allow dynamic adjustment of drivability parameters (such as drive strength or delay) based on operation frequency and signal conditions. This parameter adjustability improves signal quality across different operating conditions while maintaining a relatively simple buffer structure, resolving the contradiction between signal quality and device complexity.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If phase correction is performed by averaging signals, then phase skew is reduced, but processing time increases

Engineering Contradiction:

Improvephase accuracyVSAvoidprocessing time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The phase correction operation is performed continuously in the background during normal operation rather than as a separate processing step. The loop circuit continuously averages signals to maintain phase accuracy without interrupting or significantly delaying data processing, thus resolving the contradiction between phase accuracy and processing time.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS11824544B2Phase correction circuit, and clock buffer and semiconductor apparatus including the same

Publication Date: 2023.11.21 SK HYNIX INC

AI summary

A phase correction circuit includes a plurality of signal paths configured to transmit multi-phase signals. The phase correction circuit further includes a loop circuit coupled to the plurality of signal paths, the loop circuit configured to correct phase skew among the multi-phase signals by averaging the phases of two signals which are obtained by synthesizing a signal of each of the signal paths with another signal of a signal path different from the corresponding signal path.