Input Buffer Trim Circuit for Transition Voltage Alignment
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Solution Overview
Problem
Integrated circuit memory devices face issues with power consumption due to unintended leakage current when circuitry is suspended in high voltage states, leading to misalignment of setup and hold times in input buffers, which affects data reliability and accuracy.
Innovation Solution
The implementation of trim circuitry with serially-coupled transistors and mismatch detection operations to adjust the transition voltage of input buffers, ensuring alignment with a target transition voltage, thereby improving reliability and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If memory circuitry is suspended in high voltage states to reduce transition to normal operation, then power consumption is reduced, but unintended leakage current increases causing additional power consumption
Solution Approach 1:
The patent extracts and removes the problematic high-impedance state circuitry from the input buffer, replacing it with a controlled trim circuit that actively manages the high-impedance state. This eliminates the leakage current issue while maintaining the power-saving benefits of the suspended state.
Solution Approach 2:
The patent changes the voltage parameter of the high-impedance state from a fixed high voltage to a dynamically adjustable voltage level. By trimming the high-impedance state voltage to match the reference voltage, the patent eliminates the voltage differential that causes leakage current, thereby reducing power consumption without the harmful leakage effect.
2Adaptability or versatility
If differential amplifier transitions output voltage when input voltage signals are unequal due to voltage offset, then fabrication variability and impedance imbalance are accommodated, but setup and hold time requirements suffer significant errors
Solution Approach 1:
The patent performs a preliminary trimming operation during manufacturing or initialization to adjust the high-impedance state voltage before normal operation. This preliminary action compensates for fabrication variability and impedance imbalance, ensuring that the differential amplifier transitions at the correct voltage level and meeting setup and hold time requirements.
Solution Approach 2:
The patent implements a feedback mechanism where the high-impedance state voltage is compared against a reference voltage, and the trim circuit adjusts the high-impedance voltage based on this comparison. This feedback ensures that despite fabrication variability, the buffer transitions at the correct voltage point, maintaining precise setup and hold timing.
3Reliability
If trim circuitry is added to adjust transition voltage of input buffers, then data reliability and timing alignment are improved, but device complexity increases
Solution Approach 1:
The patent merges the trim circuit functionality with the existing input buffer structure. The trim circuit shares components and signals with the differential amplifier and high-impedance state circuitry, reducing the overall complexity increase. By integrating rather than adding separate trim functionality, the patent achieves reliable voltage adjustment with minimal additional complexity.
Data Source
AI summary
Apparatuses and methods for trimming input buffers based on identified mismatches. An example apparatus includes an input buffer having a first input stage circuit configured to receive a first signal, a second input stage circuit configured to receive a second signal, and an output stage coupled to the first and second input stage circuits and configured to provide an output signal. The first input stage circuit includes serially-coupled transistor pairs that are each coupled between the output stage and a bias voltage. Each of the plurality of serially-coupled transistors pairs are selectively enabled in response to a respective enable signal. The apparatus further including a trim circuit coupled to the first input stage circuit and comprising a plurality of programmable components. The trim circuit is configured to be programmed to provide the respective enable signals based on a detected transition voltage offset relative to a target transition voltage.