Memory Command Bus Training Using CA Pattern Parity Checks
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Solution Overview
Problem
The complexity of command bus training in memory devices, particularly for LPDDR4 and LPDDR5 technologies, results in a slow and inefficient process due to the need for extensive firmware coordination and limited sampling rates, which can lead to suboptimal signaling quality and increased risk of memory device hang or lock-up.
Innovation Solution
Implementing a command address training mode (CATM) similar to that used in DDR5 memory devices, which simplifies error checking by using parity of sampled CA values, thereby reducing the coordination work for firmware and allowing for faster and more reliable command bus training.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional command bus training methods are used with extensive firmware coordination, then comprehensive error checking can be performed, but the training process becomes slow and inefficient
Solution Approach 1:
The patent extracts the error checking function from the firmware domain and implements it directly in the memory device hardware through the TDM field. This separation allows comprehensive error checking to be performed at the device level without requiring extensive firmware coordination, thereby speeding up the training process while maintaining reliability
Solution Approach 2:
The TDM (Training Data Mode) field acts as an intermediary mechanism that enables direct communication between the memory device and controller during training. This intermediary structure allows for efficient error checking and feedback without requiring complex firmware intervention, resolving the contradiction between thorough validation and training speed
2Reliability
If traditional command bus training with extensive firmware coordination is used, then thorough validation can be achieved, but the coordination work increases complexity
Solution Approach 1:
The memory device performs self-validation during training by using its internal logic to check the TDM field against expected values. This self-service approach eliminates the need for complex external firmware coordination, reducing system complexity while maintaining thorough validation through hardware-based error detection
3Device complexity
If limited sampling rates are used in command bus training, then the training process can be simpler, but signaling quality becomes suboptimal
Solution Approach 1:
The patent replaces the mechanical limitation of sequential sampling with a parallel validation approach using the TDM field. Multiple sampling points can be validated simultaneously through hardware logic that checks TDM values, thereby improving measurement precision without increasing process complexity
Data Source
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AI summary
Techniques for command bus training to a memory device includes triggering a memory device to enter a first or a second command bus training mode, outputting a command/address (CA) pattern via a command bus and compressing a sampled CA pattern returned from the memory device based on whether the memory device was triggered to be in the first or the second command bus training mode.