Configuration Memory Bitline Override for Yield Recovery
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Solution Overview
Problem
Conventional memory yield recovery schemes are inadequate for configuration memory in integrated circuits, as they are designed for single-word accessibility and are not cost-effective for intercepting output from every configuration memory cell, leading to high yield fallout due to configuration bit failures.
Innovation Solution
The implementation of a yield recovery scheme that includes configurable circuitry, configuration memory with multiple memory cells, override circuitry, and control circuitry to assert override configuration values on bitlines and wordlines, allowing for the identification and override of faulty memory cells using a small number of redundant memory cells, thereby reducing costs and improving recovery from read-back failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory yield recovery schemes are used, then single-word accessibility is maintained, but yield fallout due to configuration bit failures remains high (30-40%)
Solution Approach 1:
The configuration memory output is segmented into multiple groups, with override circuitry selectively intercepting only the faulty group's output. This allows yield recovery without the prohibitive cost of intercepting every memory cell output, as the segmentation isolates the fault to a specific segment that can be overridden.
Solution Approach 2:
Override circuitry is introduced as an intermediary component between the configuration memory and the configurable logic. This intermediary can assert override values onto bitlines to correct faulty configuration bits, enabling yield recovery without requiring direct interception and modification of every memory cell output.
2Reliability
If override circuitry is added to intercept every configuration memory cell output, then yield recovery improves, but device cost becomes prohibitively expensive
Solution Approach 1:
The configuration memory is divided into multiple groups or segments, and override circuitry is implemented only for specific segments that are determined to be faulty. This selective segmentation approach maintains configuration bit reliability for affected areas while avoiding the prohibitive cost of implementing override circuitry for every memory cell in the entire configuration memory.
Solution Approach 2:
Override capability is applied locally only where needed - specifically to groups of configuration memory cells that are determined to be faulty. Rather than uniformly applying override circuitry across all configuration memory, the local quality principle ensures that override functionality is implemented only in the specific locations where yield recovery is necessary, reducing overall device cost.
3Reliability
If a column redundancy scheme is implemented, then yield recovery is possible, but the cost of configurably intercepting every configuration memory cell output is prohibitively expensive
Solution Approach 1:
The configuration memory output is segmented into multiple groups, and the override circuitry is designed to intercept and override only the output of faulty groups rather than every individual memory cell output. This segmented approach enables column redundancy functionality while significantly reducing the complexity and cost of output interception compared to conventional schemes.
Data Source
AI summary
A yield recovery scheme for configuration memory of an IC device includes asserting an override configuration value on a bitline of memory cells of the configuration memory, where a data node of a faulty one of the memory cells is coupled to a node of configurable circuitry of the IC device, and asserting a wordline of the faulty memory cell while the override configuration value is asserted on the bitline to couple the bitline to the node of the configurable circuitry through the faulty memory cell (i.e., to force a state of the data node to the override configuration value). An identifier of the faulty memory cell may be stored on the IC device (e.g., E-fuses), and control circuitry of the IC device may retrieve the identifier to configure override circuitry of the IC device.


