Memory Link Equalization and CDR Reset for Speed Switching
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Solution Overview
Problem
Current memory systems face challenges in increasing link speed, particularly due to issues with inter-symbol interference jitter and clock-data recovery lock processes, leading to communication errors and inefficient data transfer.
Innovation Solution
The implementation of an equalizer circuit and clock-data output circuit in a memory system that includes a continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE) to reduce inter-symbol interference jitter, along with a clock-data recovery (CDR) circuit that adjusts phase differences and resets states to prevent erroneous lock conditions, enabling seamless switching between link speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If link speed is increased in the memory system, then data transfer efficiency is improved, but inter-symbol interference jitter increases causing communication errors
Solution Approach 1:
The equalizer circuit performs preliminary compensation for inter-symbol interference before the data signal is processed further. By preemptively adjusting the distorted signal characteristics, the system prepares the signal for accurate detection at higher link speeds, preventing communication errors before they occur
Solution Approach 2:
The system implements a feedback mechanism where the detection result of predetermined data is used to determine whether to reset the clock-and-data output circuit. This feedback loop ensures that when detection fails within a predetermined period, the system automatically resets to correct erroneous lock conditions, thereby maintaining communication reliability at high link speeds
2Productivity
If link speed is increased, then data transfer efficiency is improved, but clock-data recovery lock process becomes unstable causing erroneous lock conditions
Solution Approach 1:
The system performs preliminary detection of predetermined data using the equalized signal before final data processing. This early detection step allows the system to identify and correct potential lock conditions issues before they propagate through the data processing pipeline, maintaining CDR stability at higher link speeds
Solution Approach 2:
A feedback mechanism monitors the detection result of predetermined data and automatically triggers a reset of the clock-and-data output circuit when detection fails within a predetermined period. This feedback loop corrects erroneous lock conditions, ensuring stable CDR operation even at increased link speeds
3Reliability
If equalizer circuit and CDR reset mechanisms are added, then communication reliability is improved, but device complexity increases
Solution Approach 1:
The equalizer circuit serves multiple functions: it equalizes the data signal to reduce inter-symbol interference, enables detection of predetermined data for lock condition monitoring, and supports automatic reset operations. By making the equalizer multi-functional, the system achieves improved reliability without proportionally increasing overall circuit complexity
Solution Approach 2:
The system implements self-service through automatic detection and reset mechanisms. The clock-and-data output circuit automatically detects erroneous lock conditions through predetermined data detection and self-corrects by resetting its state, eliminating the need for external intervention or complex control logic while maintaining high communication reliability
Data Source
AI summary
A memory system includes a nonvolatile memory, and a controller including an equalizer circuit and a clock-and-data output circuit. The equalizer circuit receives a first data signal from a host via a serial communication, reduces an inter-symbol interference jitter of the first data signal to generate a second data signal, and outputs the second data signal. The clock-and-data output circuit extracts a third data signal and a clock signal from the second data signal and outputs the third data signal and the clock signal. The controller executes, when a link speed with the host is switched, a process of detecting predetermined data in the third data signal based on the first data signal received from the host, and resets a state of the clock-and-data output circuit when the predetermined data is not detected within a predetermined period of time.