Memory Bank Refresh Control for Variable Word Length Access
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Solution Overview
Problem
The von Neumann bottleneck limits processing speeds due to throughput limitations in conventional computer architecture, where data transfer from memory to the processor is bottlenecked, especially in memory-intensive processes like neural networks and database operations, leading to inefficiencies in handling massive data sets.
Innovation Solution
The development of hardware chips with processing elements coupled to dedicated memory banks, allowing for partial or no refreshes, selectable sizes, and dual-port capabilities to enhance power efficiency and speed, and the use of software-configurable memory refresh control to optimize memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data transfer from memory to processor is performed using conventional computer architecture, then the system can operate with standard von Neumann architecture, but the throughput is limited causing processing speed to decrease
Solution Approach 1:
The patent merges memory and processing functions into a single integrated circuit substrate, eliminating the separation between memory and processor that causes the von Neumann bottleneck. This integration allows processing elements to directly access memory banks without external bus transfers, significantly improving both processing speed and data transfer throughput simultaneously.
Solution Approach 2:
The integrated circuit is segmented into multiple processing elements, each with dedicated memory banks, allowing parallel operations to occur simultaneously. This segmentation enables multiple data transfer and processing operations to proceed in parallel, increasing overall system throughput while maintaining high processing speeds.
2Reliability
If memory refresh operations are performed on all memory banks, then data integrity is maintained, but power consumption increases
Solution Approach 1:
The patent implements partial refresh operations where only specific memory banks or portions of memory banks are refreshed based on actual usage patterns and data retention requirements. This partial action approach maintains data integrity for actively used data while reducing power consumption by skipping refresh operations on inactive or recently accessed memory regions.
Solution Approach 2:
The memory refresh system is made dynamic by monitoring access patterns and adjusting refresh operations accordingly. The system dynamically determines which memory banks require refresh based on usage history and data importance, allowing the refresh strategy to adapt in real-time to changing workloads, thereby optimizing the balance between data integrity and power consumption.
3Ease of manufacture
If memory chip size is fixed, then manufacturing is simplified, but the chip cannot be optimized for different data set sizes
Solution Approach 1:
The memory chip is divided into multiple selectable memory banks that can be independently configured. This segmentation allows the chip to be manufactured with a fixed physical structure while enabling software-configurable selection of active memory regions, providing adaptability to different data set sizes without requiring multiple physical chip variants.
Solution Approach 2:
The memory chip incorporates dynamic configuration capabilities where memory bank activation and sizing can be changed via software control based on the specific application requirements. This dynamic reconfigurability allows a single fixed physical chip design to serve multiple purposes with varying memory requirements, maintaining manufacturing simplicity while achieving versatility.
4Device complexity
If single-port memory architecture is used, then device complexity is reduced, but parallel access capability is limited
Solution Approach 1:
The memory system is segmented into multiple independent memory banks, each with its own port capabilities. This segmentation allows different banks to be accessed simultaneously by different processing elements without requiring a complex unified multi-port architecture, thereby maintaining relative simplicity while enabling parallel access operations.
Solution Approach 2:
The memory banks are designed with universal access characteristics where each bank can serve multiple processing elements and can be configured for different access patterns. This multi-functionality allows the same memory infrastructure to support both sequential and parallel access modes, providing adaptability without significantly increasing device complexity.
Data Source
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Figure 3A
AI summary
A memory chip may include: a plurality of memory banks; a data storage configured to store access information indicative of access operations for one or more segments of the plurality of memory banks; and a refresh controller configured to perform a refresh operation of the one or more segments based, at least in part, on the stored access information.