Reconfigurable Computational Memory for In-Memory Logic
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The data bus, which transfers data between the CPU and memory array, has not kept pace with advances in semiconductor manufacturing, leading to a bottleneck that limits the further increase in processing speed due to the physical constraints of smaller memory arrays and larger data storage needs.
Innovation Solution
A non-Von Neumann architecture computation system that incorporates a memory module capable of performing logic operations using ferroelectric field effect transistors (FETs) and resistive storage devices, allowing data processing within the memory module, thereby reducing the need for data transfer to the CPU and enhancing efficiency in terms of energy and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is transferred between CPU and memory array through data bus, then data storage capacity can be increased, but processing speed is limited due to data bus bottleneck
Solution Approach 1:
The patent combines memory storage functions with logic processing functions into a single memory device. The memory device includes memory cells for data storage and logic circuitry for performing logical operations directly on the stored data, eliminating the need for separate CPU processing and data transfer through data bus.
Solution Approach 2:
The patent introduces a reconfigurable logic unit as an intermediary between the memory cells and the external data bus. This logic unit can be configured to perform different logical operations and processes data locally within the memory device, reducing data transfer requirements and improving processing speed.
2Area of stationary object
If memory arrays are made physically smaller to increase storage density, then storage capacity per area increases, but data transfer bottleneck worsens
Solution Approach 1:
The patent transitions from a two-dimensional planar memory architecture to a three-dimensional stacked architecture. Multiple memory layers are stacked vertically, each layer containing memory cells and associated logic units. This vertical stacking increases storage density without proportionally increasing the footprint area, and allows for local processing within each layer.
Solution Approach 2:
The patent divides the memory device into multiple independent memory layers, with each layer containing memory cells and reconfigurable logic units. This segmentation allows parallel processing across layers and reduces the need for data transfer between layers, improving overall productivity while maintaining compact form factor.
3Extent of automation
If data processing is performed in CPU, then computation capability is provided, but data transfer between CPU and memory creates latency
Solution Approach 1:
The patent enables the memory device to perform logical operations on its own stored data without requiring external CPU intervention. The reconfigurable logic units within the memory device can execute logical operations directly on the data in memory cells, providing self-service computation capability and eliminating data transfer latency for these operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces data transfer between the memory module and the CPU, improving processing efficiency and overcoming the bottleneck by enabling logic operations within the memory module, thus enhancing performance and reducing latency.
Implementation Method 1
The gate structure of the FET includes a ferroelectric layer lying between the gate electrode and the conduction channel
Data Source
AI summary
A memory device, an operation method of a memory cell in a memory device and a semiconductor die are provided. A computational memory cell in the memory device includes: a field effect transistor (FET), with a changeable threshold voltage; and resistive storage devices, connected by a common terminal coupled to a source/drain terminal of the FET. By altering the threshold voltage of the FET, a logic function of the computational memory cell can be changed. During a logic operation, inputs are provided to the computational memory cell as resistance states of the resistive storage devices, and a current passing through a conduction channel of the FET is functioned as an output for the logic operation.