Multi-Inverter NVM Sense Circuit Without Reference Read Errors
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Solution Overview
Problem
Current resistive nonvolatile memory (NVM) technologies face read errors due to high variability in reference parameters generated by reference circuits, caused by process and thermal variations, leading to inaccurate bit value determination during read operations.
Innovation Solution
A high-accuracy reference-free multi-inverter sense circuit is introduced, comprising multiple field effect transistors (FETs) connected in parallel with inverters between the data line and the gates of the FETs, which detects voltage drops on the data line within a predetermined period to determine the logic value of stored bits without relying on a reference parameter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reference parameter is used for read operations, then the read operation can be performed, but the reference parameter variability due to process and thermal variations leads to read errors
Solution Approach 1:
The patent removes the reference parameter and reference circuit from the sensing system entirely. Instead of comparing the memory cell output to a reference voltage or current, the invention uses a differential sensing approach where two sense amplifiers simultaneously sense the bit line and complement bit line, eliminating the need for a separate reference parameter generation circuit and its associated variability issues.
Solution Approach 2:
The patent creates a complementary copy of the sensing path by implementing both a sense amplifier for the bit line and a sense amplifier for the complement bit line. These two sensing paths operate in parallel and are differentially compared, allowing the system to detect voltage drops without requiring an external reference parameter.
2Ease of operation
If a reference circuit is used to generate reference parameter, then read operation can be performed, but the reference circuit occupies additional area and increases device complexity
Solution Approach 1:
The patent extracts and removes the reference circuit from the memory structure. By using differential sensing with complementary bit lines, the system eliminates the need for separate reference voltage or reference current generation circuits, thereby reducing device complexity and freeing up area.
Solution Approach 2:
The sense amplifiers serve multiple functions: they simultaneously sense the voltage on the bit line and the complement bit line, perform differential comparison, and drive the output. This multi-functionality eliminates the need for separate reference circuit components.
3Measurement precision
If a reference parameter is used for sensing, then the sensing operation can be performed, but process and thermal variations cause reference parameter variability
Solution Approach 1:
The patent removes the reference parameter from the sensing equation entirely. By using differential sensing where both the bit line and complement bit line are sensed simultaneously and compared, the system eliminates the reference parameter that would otherwise be subject to process and thermal variations.
Solution Approach 2:
The differential sensing mechanism provides implicit feedback by continuously monitoring both the bit line and complement bit line voltages and comparing them in real-time. This allows the system to automatically compensate for variations without requiring a stable reference parameter, as the comparison is made between two similarly affected signals.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the accuracy of bit value detection, reducing read errors by utilizing redundant inverters and FETs to reliably capture voltage drops, even in the presence of process and thermal variations, without the need for a reference parameter.
Implementation Method 1
the output voltage on the output node at the end of the predetermined period of time will be at either a first voltage level or a second voltage level that is greater than the first voltage level. More particularly, at the end of the predetermined period of time, the output voltage will be at the first voltage level if a voltage drop on the data line causes at least one of the multiple inverters to switch output states
Data Source
AI summary
Disclosed is a memory structure with reference-free single-ended sensing. The structure includes an array of non-volatile memory (NVM) cells (e.g., resistance programmable NVM cells) and a sense circuit connected to the array via a data line and a column decoder. The sense circuit includes field effect transistors (FETs) connected in parallel between an output node and a switch and inverters connected between the data line and the gates of the FETs, respectively. To determine the logic value of a stored bit, the inverters are used to detect whether or not a voltage drop occurs on the data line within a predetermined period of time. Using redundant inverters to control redundant FETs connected to the output node increases the likelihood that the occurrence of the voltage drop will be detected and captured at the output node, even in the presence of process and/or thermal variations. Also disclosed is a sensing method.