DAC Output Synchronization Using Internal Delay Alignment
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Solution Overview
Problem
High-speed digital/analog converters in applications like matrix antennas face challenges in synchronizing internal clocks and aligning data due to high sampling frequencies and physical distance issues, leading to difficulties in evaluating propagation delays and potential jitter problems in existing synchronization methods.
Innovation Solution
A method involving an external synchronization signal and internal synchronization signal generation within each converter, with a control unit providing a common reference clock and applying delays to each converter based on clock tick counts to align data on the same active edge of the clock, using a cascade configuration of synchronization circuits and counters to synchronize data across multiple converters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an external synchronization signal is sent to all converters with designed distribution paths, then the converters can be synchronized, but precise evaluation of propagation delays becomes increasingly difficult when working frequencies are above 100 MHz
Solution Approach 1:
Each converter autonomously generates its own internal synchronization signal based on the external synchronization signal and common reference clock, eliminating the need for complex external delay evaluation. The converter self-adjusts by counting clock cycles between start signal and internal synchronization signal generation, making the system self-calibrating without requiring precise external measurement of propagation delays
Solution Approach 2:
The system implements feedback by having each converter count the number of clock cycles between receiving the start signal and generating its internal synchronization signal. This count is used to calculate the delay Ri that needs to be applied to each converter, creating a closed-loop synchronization system that automatically compensates for propagation delays without requiring external measurement
2Reliability
If the sampling clock is modified to synchronize converters, then converter synchronization is achieved, but the signal quality degrades due to jitter problems
Solution Approach 1:
The synchronization function is separated from the sampling clock function. The common reference clock continues to provide stable sampling timing, while a separate internal synchronization signal generated from the external synchronization signal handles converter synchronization. This segmentation prevents jitter from affecting signal quality while maintaining synchronization
Solution Approach 2:
An intermediate internal synchronization signal is introduced as a mediator between the external synchronization signal and the converter operation. This intermediate signal absorbs the synchronization requirements without directly modifying the sampling clock, thereby preventing jitter while achieving converter synchronization
3Reliability
If subdivisions of sampling frequency and master/slave system are used for synchronization, then converter synchronization is achieved, but temperature tolerance is limited and clock management becomes complicated
Solution Approach 1:
The common reference clock serves multiple functions simultaneously: it provides the sampling clock for conversion operations and serves as the timing basis for synchronization signal generation. This multi-functionality eliminates the need for separate clock management systems while maintaining both conversion and synchronization operations
Solution Approach 2:
Instead of using frequency subdivisions and master/slave configurations, the system changes the approach by using a single common reference clock frequency and varying only the phase/delay parameters of individual converters through calculated delay Ri values. This parameter-based approach simplifies clock management while maintaining synchronization across all converters
Data Source
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AI summary
Method for synchronising analogue data (Data_ana1, Data_ana2) at the output of a plurality of digital/analogue converters (DAC), comprising at least one conversion core (C1, C2), on an active edge of a common reference clock (Clk), the method comprising the following steps: a) supplying an external synchronisation signal (SYNC_ext) to at least one converter, and supplying a signal of the common reference clock to the plurality of converters; b) generating within each converter an internal synchronisation signal (SYNC_int), such that all the internal synchronisation signals are aligned on an active edge of the common reference clock; c) for each of the converters, generating a start signal (START1, START2) which represents the start of the sending of digital data and counting a number of clock strokes until the internal synchronisation signal is generated and; d) applying a delay Ri (R1, R2) to each converter core, the delay being equal to the difference between the highest number counted in step c) and the number counted for the core. Device for implementing such a method.