Resistive Configuration Bit Circuit for Secure FPGA Boot
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Solution Overview
Problem
Conventional configuration bit storage in field-programmable gate arrays (FPGAs) faces issues with security, scalability, and performance due to the use of external non-volatile memory, which can be vulnerable to radiation and requires significant peripheral circuitry, making it unsuitable for smaller-scale technologies.
Innovation Solution
Implementing magnetoresistive random-access memory (MRAM) or resistive random-access memory (ReRAM) as non-volatile memory within the FPGA, allowing for multi-time or one-time programmable configuration bits with reduced circuitry needs and improved security by storing configuration values internally.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external non-volatile memory is used to store configuration bits, then configuration information can be stored, but security is compromised and the system becomes vulnerable to radiation disruption
Solution Approach 1:
The patent extracts the configuration bit storage function from external non-volatile memory and relocates it to internal non-volatile memory within the FPGA device. This extraction eliminates the security risks and radiation vulnerability associated with external memory while maintaining the non-volatile storage capability.
Solution Approach 2:
The internal non-volatile memory structure is designed to serve multiple functions: storing configuration bits, providing non-volatile persistence, and enabling secure operation. This multi-functional approach replaces the need for separate external memory components.
2Loss of time
If external non-volatile memory is used for configuration storage, then configuration bits can be stored, but boot time increases and performance decreases
Solution Approach 1:
The patent implements preliminary action by pre-loading configuration bits into internal non-volatile memory during manufacturing or initialization, so that the FPGA can boot directly from this internal storage without requiring external memory access during startup, thereby reducing boot time.
3Reliability
If conventional non-volatile memory (Flash) is used in the FPGA, then non-volatile storage is achieved, but device complexity increases due to significant additional circuitry
Solution Approach 1:
The patent changes the physical and operational parameters of the non-volatile memory by using magnetoresistive or resistive memory elements instead of conventional Flash memory. This parameter change enables non-volatile storage with significantly reduced circuitry requirements and improved scalability to smaller technology nodes.
Solution Approach 2:
The patent substitutes the mechanical/electrical structure of conventional Flash memory with a resistive memory structure based on magnetic or resistive effects. This substitution eliminates the need for complex charge trapping and tunneling mechanisms, simplifying the overall circuitry while maintaining non-volatile functionality.
4Reliability
If conventional non-volatile memory is used in the FPGA, then non-volatile storage is achieved, but scalability to smaller technologies is prevented
Solution Approach 1:
The patent changes the fundamental operating parameters and physical structure of the memory to resistive or magnetic effects, which can be implemented at much smaller dimensions than conventional Flash memory. This enables scalability to advanced technology nodes while maintaining non-volatile storage capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances security, reduces circuitry requirements, and enables scalability to smaller manufacturing scales by eliminating the need for external memory and simplifying peripheral components, thus improving boot time and reducing vulnerability to disruptions.
Implementation Method 1
magnetoresistive random-access memory (MRAM) or resistive random-access memory (ReRAM)
Implementation Method 2
resistive random-access memory (ReRAM)
Data Source
AI summary
The present disclosure is drawn to, among other things, a configuration bit including at least four resistive elements and a voltage amplifier. At least two first resistive elements may be electrically connected in series via a first electrode and at least two second resistive elements may be electrically connected in series via a second electrode. The at least two first resistive elements may be electrically connected in parallel to the at least two second resistive elements via a third electrode and a fourth electrode. The first electrode and the second electrode may be electrically connected to a voltage supply. The third electrode and the fourth electrode may be electrically connected to an input of the voltage amplifier.