Symmetric Clock Converting Circuit for Skew and Duty Error Reduction
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Solution Overview
Problem
Memory devices face challenges in processing high-frequency clock signals due to skew and duty errors, which can lead to abnormal operations and reduced data reliability.
Innovation Solution
A clock converting circuit is designed with a symmetrical output stage and switches that operate based on specific logic states of input clocks, generating output clocks with coordinated edge types to mitigate skew and duty errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a clock signal is processed at high frequency in memory device, then processing speed is improved, but skew and duty errors increase causing abnormal operation
Solution Approach 1:
The clock signal processing is divided into multiple stages: input stage, duty conversion stage, and output stage. Each stage handles specific aspects of clock signal transformation, allowing high-frequency processing while maintaining reliability through structured segmentation of functions.
Solution Approach 2:
The patent employs asymmetric switch configurations in the duty conversion stage where different switches (first, second, third switches) are controlled by different logic states of input clocks. This asymmetric design enables precise control of clock edge types to eliminate skew and duty errors while maintaining high-frequency operation.
2Adaptability or versatility
If duty conversion is performed on clock signal, then clock signal adaptability is improved, but skew and duty errors are introduced
Solution Approach 1:
The circuit uses feedback mechanisms where the logic states of input clocks continuously control the switching actions. The first switch responds to first logic state, second switch to second logic state, and third switch to opposite logic state, creating a feedback-controlled system that maintains precision while adapting to different clock signals.
Solution Approach 2:
The patent changes the duty parameter of the clock signal through controlled switching operations. By manipulating which switches are activated based on input clock logic states, the circuit transforms the duty cycle while maintaining precise timing relationships, thus adapting the clock signal without introducing errors.
3Device complexity
If asymmetric output stage is used in clock converting circuit, then device complexity is reduced, but skew and duty errors increase
Solution Approach 1:
The output stage employs an asymmetric configuration of switches and control logic that is deliberately designed to produce symmetric output clock edges. The first and second switches are controlled by opposite logic states, while the third switch is controlled by the opposite logic state of the second input clock, creating a balanced output despite asymmetric internal structure.
Solution Approach 2:
The circuit inverts the control logic for different switches to achieve symmetric output. The first switch operates on first logic state while the second switch operates on second logic state (opposite to first), and the third switch operates on opposite logic state of second input clock. This inversion strategy eliminates skew and duty errors while maintaining relatively simple circuit structure.
Data Source
AI summary
Disclosed is a clock converting circuit, which includes a first switch that is connected between a first input node for receiving a second input clock and a first node and operates in response to a first logic state of a first input clock, the second input clock delayed with respect to the first input clock as much as 90 degrees, a second switch that is connected between a second input node for receiving the first input clock and a second node and operates in response to a second logic state of the second input clock, and a third switch that is connected between the second node and a ground node and operates in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.