Neuromorphic Memory Array Redundancy for Fault Repair
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Solution Overview
Problem
Neuromorphic devices face challenges in detecting and repairing faults in their memory arrays, which can lead to performance degradation and increased power consumption, affecting their ability to execute deep learning operations accurately.
Innovation Solution
The neuromorphic device incorporates a first and second memory cell array with redundancy lines and word lines, along with an analog-to-digital converter (ADC) circuit, to detect faults and replace faulty sub-arrays with redundancy sub-arrays, ensuring continuous operation and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fault detection and repair mechanisms are implemented in neuromorphic devices, then reliability is improved, but device complexity increases
Solution Approach 1:
The memory array is divided into multiple sub-arrays, each with its own fault detection and repair capabilities. This segmentation allows independent management of fault handling in each sub-array, reducing the overall complexity burden on the entire system while maintaining high reliability through distributed fault management.
Solution Approach 2:
Redundant memory cells and lines are pre-configured within each sub-array before faults occur. When a fault is detected, the system can immediately switch to the pre-prepared redundant components without requiring complex real-time reconfiguration, thus improving reliability while keeping the repair mechanism relatively simple.
2Reliability
If redundant memory cells and lines are added for fault repair, then reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The redundant word lines, bit lines, and source lines are designed to serve multiple sub-arrays universally. A single redundant line can replace faulty lines in different sub-arrays, reducing the total number of redundant components needed and lowering manufacturing precision requirements while maintaining fault tolerance capabilities.
Solution Approach 2:
When faults occur in memory cells, the system discards the faulty cells and recovers functionality by activating redundant lines. This approach allows the system to tolerate manufacturing defects by simply switching to backup components rather than requiring perfect manufacturing precision for all components.
3Reliability
If fault detection mechanisms are implemented, then reliability is improved, but power consumption increases
Solution Approach 1:
Fault detection is performed periodically rather than continuously, allowing the system to monitor the health of memory sub-arrays at scheduled intervals. This periodic detection approach maintains reliability by catching faults when they occur while significantly reducing power consumption compared to continuous monitoring.
Solution Approach 2:
The fault detection mechanism utilizes existing read operations and data patterns to detect faults without requiring separate dedicated detection circuits. By leveraging the normal operational data flow for fault detection, the system improves reliability while minimizing additional power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables effective fault detection and repair, maintaining the accuracy of deep learning operations while reducing power consumption by utilizing redundancy sub-arrays to replace faulty ones, thereby enhancing the reliability and efficiency of the neuromorphic device.
Implementation Method 1
first resistive memory cells connected to word lines, bit lines, and source lines... configured to store weight data corresponding to a weight of a neural network in the first resistive memory cells, and generate a plurality of read currents based on input signals and the weight data
Implementation Method 2
an analog to digital converter (ADC) circuit configured to convert the plurality of read currents into a plurality of digital signals based on the plurality of reference currents
Data Source
AI summary
A neuromorphic device includes a memory cell array including first resistive memory cells connected to word lines, bit lines and source lines, second resistive memory cells connected to the word lines, at least one redundancy bit line and at least one redundancy source line, third resistive memory cells connected to at least one redundancy word line, the bit lines and the source lines. The memory cell array stores data corresponding to a weight of a neural network in the first resistive memory cells, and is configured to generate a plurality of read currents based on input signals and the data. The neuromorphic device further includes an analog to digital converter (ADC) circuit configured to convert the plurality of read currents into a plurality of digital signals.