Clock Buffer Repeater Asymmetry for Memory Duty Error Correction
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Solution Overview
Problem
Existing memory devices suffer from duty errors in clock signals due to Process, Voltage, Temperature (PVT) fluctuations, which reduce the reliability of the clock and overall system performance.
Innovation Solution
Incorporating a clock buffer with a series of clock repeaters, each comprising a pair of inverters with intentionally imbalanced driving capabilities between PMOS and NMOS transistors, where the directions of imbalance are opposite to cancel out duty errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock buffers with balanced PMOS and NMOS transistors are used, then the circuit design is simple, but duty errors accumulate due to PVT fluctuations
Solution Approach 1:
The patent applies asymmetry by configuring clock repeaters with intentionally imbalanced PMOS and NMOS transistor driving capabilities. Specifically, odd-numbered clock repeaters have PMOS transistors with stronger driving capability than NMOS transistors, while even-numbered clock repeaters have NMOS transistors with stronger driving capability than PMOS transistors. This asymmetric configuration compensates for duty errors caused by PVT fluctuations, resolving the contradiction between reliability and complexity by using controlled asymmetry to achieve duty cycle correction.
Solution Approach 2:
The patent employs parameter changes by adjusting the driving capability parameters of PMOS and NMOS transistors in clock repeaters. The width-to-length ratios (W/L) of transistor channels are specifically designed to create imbalanced driving capabilities. By changing these physical parameters of the transistors, the patent achieves duty error correction without requiring complex external control circuits, thus improving reliability while maintaining manageable device complexity.
2Reliability
If clock repeaters with imbalanced driving capabilities are used to correct duty errors, then duty cycle accuracy improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies segmentation by dividing the clock buffer into multiple discrete clock repeaters arranged in series. Each clock repeater is further segmented into separate PMOS and NMOS transistor components with independently controllable driving capabilities. This segmentation allows the duty error correction function to be distributed across multiple units, where each unit contributes to the overall correction. The odd-even numbering scheme segments the correction task into alternating patterns, making the manufacturing precision requirements more manageable by localizing the imbalance control to specific repeater units rather than requiring precise balance across the entire buffer.
3Measurement precision
If training and adjustment procedures are implemented, then duty cycle monitoring accuracy improves, but operation time increases
Solution Approach 1:
The patent applies preliminary action by pre-configuring the clock repeaters with imbalanced driving capabilities during the manufacturing process. The odd-numbered repeaters are pre-set with PMOS-dominant characteristics, while even-numbered repeaters are pre-set with NMOS-dominant characteristics. This preliminary configuration establishes the duty error correction mechanism before the device enters operation. While training procedures are still performed to monitor and fine-tune the duty cycle, the pre-configured asymmetric structure provides the foundation for correction, reducing the time required compared to systems that must establish balance dynamically during operation.
Data Source
AI summary
A memory device includes a memory cell array having memory cells connected to wordlines and bitlines, and a clock buffer receiving a clock signal for performing a read operation or a write operation on at least one of the memory cells. The clock buffer includes a plurality of serially connected clock repeaters, and the plurality of clock repeaters have at least one pair of clock repeaters having different imbalanced driving capabilities.