Reconfigurable Processing-in-Memory Logic for Parallel Throughput

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Solution Overview

Problem

Existing computer systems face challenges in improving throughput while minimizing energy consumption and cost, as increasing processing cores leads to exorbitant costs and inefficiencies in parallel computation implementations.

Innovation Solution

Implementing reconfigurable processing-in-memory (PIM) logic within memory devices equipped with logic arrays and control blocks, utilizing pull networks to control memory arrays and manage computations, enabling highly parallel computational pipelines without the need for excessive processing cores.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the number of processing cores is increased to improve throughput, then computational throughput is improved, but system cost and energy consumption increase exorbitantly

Engineering Contradiction:
Improvecomputational throughputVSAvoidenergy consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent merges memory storage and logic processing functions into a single integrated structure. Memory cells are equipped with pull-down networks and pull-up networks that can perform logical operations directly on stored data, eliminating the need for separate processing cores and reducing energy consumption associated with data movement between memory and processing units.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The memory cells are designed to serve multiple functions: they can store data and simultaneously perform logical operations on that data. The pull networks can be configured to implement different logic functions, making the memory system universal and adaptable to various computational tasks without requiring additional specialized processing units.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If the number of processing cores is increased to improve throughput, then computational throughput is improved, but system cost increases exorbitantly

Engineering Contradiction:
Improvecomputational throughputVSAvoidsystem cost
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges memory storage and logic processing functions into a single integrated structure. Memory cells are equipped with pull-down networks and pull-up networks that can perform logical operations directly on stored data, eliminating the need for separate processing cores and reducing energy consumption associated with data movement between memory and processing units.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The memory cells are designed to serve multiple functions: they can store data and simultaneously perform logical operations on that data. The pull networks can be configured to implement different logic functions, making the memory system universal and adaptable to various computational tasks without requiring additional specialized processing units.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If specialized processors are used to achieve high parallelism, then computational efficiency for parallel applications is improved, but system cost and energy consumption increase

Engineering Contradiction:
Improveparallel computational efficiencyVSAvoidenergy consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The memory system performs computations on data while it is stored, eliminating the need to move data to separate processing units and back. The pull networks within memory cells autonomously perform logical operations on stored data, reducing energy consumption associated with data movement and enabling efficient parallel processing without specialized processors.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent merges memory storage and logic processing functions into a single integrated structure. Memory cells are equipped with pull-down networks and pull-up networks that can perform logical operations directly on stored data, eliminating the need for separate processing cores and reducing energy consumption associated with data movement between memory and processing units.

Inventive Principle:
Principle #5Merging (Combining)

4Productivity

If specialized processors are used to achieve high parallelism, then computational efficiency for parallel applications is improved, but system cost increases

Engineering Contradiction:
Improveparallel computational efficiencyVSAvoidsystem cost
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The memory system performs computations on data while it is stored, eliminating the need to move data to separate processing units and back. The pull networks within memory cells autonomously perform logical operations on stored data, reducing energy consumption associated with data movement and enabling efficient parallel processing without specialized processors.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent merges memory storage and logic processing functions into a single integrated structure. Memory cells are equipped with pull-down networks and pull-up networks that can perform logical operations directly on stored data, eliminating the need for separate processing cores and reducing energy consumption associated with data movement between memory and processing units.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11887693B2Reconfigurable processing-in-memory logic
Publication Date: 2024.01.30 LODESTAR LICENSING GROUP LLC
  • US11887693B2 patent drawing
  • US11887693B2 patent drawing
  • US11887693B2 patent drawing

AI summary

An example system implementing a processing-in-memory pipeline includes: a memory array to store data in a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; a logic array coupled to the memory array, the logic array to implement configurable logic controlling the plurality of memory cells; and a control block coupled to the memory array and the logic array, the control block to control a computational pipeline to perform computations on the data by activating at least one of: one or more bitlines of the plurality of bitlines or one or more wordlines of the plurality of wordlines.