Memory Bank Transfer Bus for Faster Low-Power Data Movement
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices face inefficiencies in data transfer between banks, requiring external buses and consuming significant power and time, especially in processing-in-memory (PIM) implementations where data operations span multiple banks.
Innovation Solution
The implementation of a bank-to-bank transfer (BBT) bus separate from the internal bus allows for parallel, optimized data transfer between memory banks, minimizing power consumption and transfer time by selecting the shortest path, thereby reducing the reliance on external data buses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If data transfer between memory banks uses external buses, then data can be transferred between banks, but power consumption increases and transfer time increases
Solution Approach 1:
The patent divides the data transfer function into two separate paths: an internal bus for transfers within the same memory device and an external bus for transfers between different memory devices. This segmentation allows the system to use the more efficient internal path whenever possible, reducing power consumption and transfer time for intra-device bank-to-bank transfers.
Solution Approach 2:
The patent introduces an intermediary component (the internal bus) that facilitates direct data transfer between memory banks within the same memory device. This intermediary eliminates the need for data to traverse external buses for intra-device transfers, thereby reducing power consumption and transfer time while maintaining the ability to use external buses when inter-device transfer is required.
2Loss of time
If data transfer between memory banks uses external buses, then data can be transferred between banks, but transfer time increases
Solution Approach 1:
The patent segments the data transfer functionality into internal and external bus paths, allowing the system to select the appropriate path based on whether the transfer is within the same memory device or between different devices. This segmentation enables faster transfer times for intra-device operations by using the dedicated internal bus path.
Solution Approach 2:
The internal bus acts as an intermediary that provides a direct, high-speed data transfer path between memory banks within the same memory device. This intermediary structure eliminates the need for data to exit and re-enter the device through external buses, significantly reducing transfer time for intra-device transfers.
3Productivity
If a separate bank-to-bank transfer bus is implemented, then data transfer efficiency improves, but device complexity increases
Solution Approach 1:
The patent implements segmentation by creating distinct internal and external bus structures for data transfer. The internal bus is specifically designed for efficient bank-to-bank transfers within the same memory device, while the external bus handles inter-device communication. This segmentation improves data transfer efficiency for the common case of intra-device transfers.
Solution Approach 2:
The internal bus structure is designed to be universal for all bank-to-bank transfers within the memory device, providing a single optimized path that can handle any inter-bank transfer scenario. This multi-functional design improves efficiency without requiring separate dedicated paths for each possible transfer scenario.
Data Source
AI summary
The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.