Self-Shielding Delay Circuit for Multi-Phase Memory Clock Accuracy
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Solution Overview
Problem
As clock signal frequencies in chips increase, the anti-interference ability of chips worsens, leading to higher error probabilities in signal processing. This is particularly challenging in memory integrated circuits where precise signal handling is critical.
Innovation Solution
A delay circuit is introduced, comprising a self-shielding circuit and a delay component. The self-shielding circuit receives an initial command signal and N initial clock signals, registers the command signal based on the earliest triggering clock signal, shields other clock signals, and outputs intermediate command signals. The delay component then delays these intermediate signals to produce a delayed command signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the frequency of clock signal is increased to improve chip performance, then productivity is improved, but reliability deteriorates due to worse anti-interference ability and higher error probability
Solution Approach 1:
The patent segments the clock signal processing by introducing multiple phase-shifted clock signals (N initial clock signals with different phases) and using a self-shielding circuit to divide the registration process into N separate registration circuits. Each registration circuit processes one phase of the clock signal independently, allowing the system to operate at high frequency while maintaining reliability through phase-divided processing.
Solution Approach 2:
The patent applies preliminary action by using the self-shielding circuit to pre-process and select the earliest triggering clock signal before the actual registration occurs. The self-shielding circuit identifies and selects the valid clock signal phase in advance, preventing interference from other phases during the registration process, thus ensuring accurate signal processing at high frequencies.
2Productivity
If multiple clock signals are used to process command signals, then productivity is improved through parallel processing, but reliability deteriorates due to errors caused by simultaneous clock signal actions
Solution Approach 1:
The patent segments the clock signal processing by introducing multiple phase-shifted clock signals (N initial clock signals with different phases) and using a self-shielding circuit to divide the registration process into N separate registration circuits. Each registration circuit processes one phase of the clock signal independently, allowing the system to operate at high frequency while maintaining reliability through phase-divided processing.
Solution Approach 2:
The patent introduces a self-shielding circuit as an intermediary between the multiple clock signals and the registration circuits. This intermediary component manages the interaction between N clock signals by selecting the earliest triggering signal and shielding others, preventing direct interference while enabling parallel processing capabilities.
3Reliability
If frequency division clock signal is used to reduce error probability, then reliability is improved, but productivity deteriorates due to lower operating frequency
Solution Approach 1:
The patent applies periodic action by using N initial clock signals with different phases that are derived from frequency division of the original high-frequency clock signal. These phase-shifted clock signals are distributed at regular intervals throughout the clock period, enabling the system to process signals at high frequency equivalent to the original clock while actually operating at lower frequency division, thus improving reliability without sacrificing productivity.
Solution Approach 2:
The patent transitions from time-domain frequency division to phase-domain parallel processing. Instead of processing signals sequentially at lower frequency, the system uses multiple phase-shifted clock signals to process different portions of the signal simultaneously in the phase dimension, achieving high-speed processing with improved reliability through the self-shielding mechanism.
Data Source
AI summary
A delay circuit includes a self-shielding circuit and a delay. The self-shielding circuit is configured to: receive an initial command signal and N initial clock signals, register the initial command signal according to a first initial clock signal among the N initial clock signals that triggers the initial command signal at earliest, shield other N−1 second initial clock signals, and output N intermediate command signals, where N is an integer greater than or equal to 2, and the N initial clock signals have a same frequency and different phases. The delay is electrically connected to the self-shielding circuit and is configured to: receive the N intermediate command signals and the N initial clock signals, and delay and output the N intermediate command signals to obtain a delayed command signal. Thus, the accuracy of signal processing can be improved.