DRAM Command Decoding Circuit for Multi-Cycle ODT Accuracy
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Solution Overview
Problem
Current decoding processes in dynamic random access memory (DRAM) face challenges with incorrect decoding in the second cycle of non-target on-die termination commands, leading to a low decoding success rate.
Innovation Solution
A signal processing circuit is introduced, featuring a command decoding circuit with a preprocessing circuit that generates chip select identifier signals based on previous cycle signals, and an operation circuit that determines the generation of decoded commands based on the current and previous cycle signal states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a current decoding process is used in DRAM, then the decoding process is simple, but incorrect decoding occurs in the second cycle of non-target on-die termination commands
Solution Approach 1:
The patent applies preliminary action by generating chip select identifier signals in advance based on previous cycle signals before the current decoding operation. The preprocessing circuit creates these identifier signals beforehand, which are then used by the operation circuit to determine whether to generate decoded commands. This advance preparation prevents incorrect decoding in the second cycle of non-target on-die termination commands while maintaining a manageable circuit complexity through structured signal preparation.
2Reliability
If signal processing is performed only in the current cycle, then the processing speed is fast, but decoding correctness cannot be ensured across multiple cycles
Solution Approach 1:
The patent segments the decoding process into distinct functional components: a preprocessing circuit that handles signal preparation by generating chip select identifier signals, and an operation circuit that performs the actual decoding determination. This segmentation allows signal processing to span multiple cycles appropriately - the preprocessing occurs in previous cycles while the operation circuit uses these prepared signals for correct decoding decisions, thereby ensuring decoding correctness without excessive time loss.
3Reliability
If chip select signals from multiple previous cycles are processed, then decoding accuracy improves, but the circuit complexity increases
Solution Approach 1:
The patent applies universality by designing the preprocessing circuit to handle multiple previous cycles of chip select signals through a unified approach. The circuit generates chip select identifier signals that can be used across different cycle scenarios (first cycle, second cycle, non-target on-die termination commands) without requiring separate processing paths for each case. This multi-functional design improves decoding success rate while controlling circuit complexity through standardized signal processing logic.
Data Source
AI summary
Embodiments of the present disclosure provide a signal processing circuit and a memory. A command decoding circuit is included, which includes: a preprocessing circuit, configured to: receive a first chip select signal corresponding to previous one cycle of a current cycle corresponding to a current chip select signal and a first command signal corresponding to the previous one cycle of the current cycle corresponding to signal, and perform a logical operation on the first chip select signal and the first command signal to generate a first chip select identifier signal; and an operation circuit, connected to the preprocessing circuit, and configured to: receive the first chip select identifier signal and the current chip select signal, and generate a decoded command corresponding to the current chip select signal when the current chip select signal is in an enabled state and the first chip select identifier signal is in a disabled state.