High-Resolution Phase Correction Circuit for Fine Clock Alignment
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Solution Overview
Problem
As semiconductor devices operate at higher speeds, the shorter toggle period of clock signals requires finer tuning of clock signal phases to minimize phase differences and errors in communication signals, which existing technologies struggle to achieve effectively.
Innovation Solution
A high-resolution phase correcting circuit and phase interpolating device are developed, incorporating a delay circuit, load capacitor, and fine-tuning circuits that adjust the clock signal phase based on control signals, allowing for precise phase correction and interpolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operating speed of the semiconductor device is increased, then the productivity is improved, but the toggle period of the clock signal becomes shorter making phase tuning more difficult
Solution Approach 1:
The phase correction range is divided into multiple segments using a tree-structured correction path. The total phase correction range is segmented into coarse correction stages and fine correction stages, allowing progressive refinement of phase alignment without requiring the entire correction range to operate at full resolution simultaneously.
Solution Approach 2:
The phase correction mechanism dynamically adjusts the correction amount based on the detected phase difference. The correction amount is determined adaptively according to the magnitude of the phase error, applying larger corrections when needed and finer adjustments when approaching the target phase alignment.
2Manufacturing precision
If a conventional phase correction circuit is used, then the device complexity is low, but the phase correction resolution is insufficient for high-speed operation
Solution Approach 1:
The phase correction function is segmented across multiple correction paths arranged in a tree structure. Each path handles a specific portion of the correction range, allowing the system to achieve high resolution through coordinated operation of simpler sub-circuits rather than requiring a single complex high-resolution circuit.
Solution Approach 2:
The phase correction is performed in stages, applying partial corrections sequentially along different paths. The coarse correction paths provide initial alignment, and fine correction paths provide precise adjustment, achieving overall high resolution through cumulative partial actions rather than requiring all correction capability in a single stage.
Data Source
AI summary
A phase correcting circuit includes a delay circuit that receives an input clock signal and delays the input clock signal as much as a first delay time to output an output clock signal to a 0-th node, a first fine tuning circuit, and a second fine tuning circuit. The first fine tuning circuit includes a first terminal connected with the 0-th node, a second terminal receiving a first control signal, and a third terminal, and the second fine tuning circuit includes a fourth terminal connected with the third terminal, a fifth terminal receiving a second control signal, and a sixth terminal connected with a load capacitor. In response to the first control signal, the output clock signal may be further delayed as much as a second delay time shorter than the first delay time. In response to the second control signal, the output clock signal may be advanced as much as a third delay time shorter than the first delay time.