Hybrid Memory Array Layout for Density and Bit Accuracy
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Solution Overview
Problem
Existing memory systems face challenges in achieving better memory performance, capacity, and power efficiency due to the slowing pace of Moore's Law, leading to reduced spatial efficiency and density.
Innovation Solution
The proposed memory structure incorporates a combination of single-memory-element and multiple-memory-element structures, where least significant bits (LSB) are stored using multiple-memory-element structures and most significant bits (MSB) are stored using single-memory-element structures, optimizing memory-element-to-transistor ratio to enhance spatial efficiency and density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If single-memory-element structures are used for all bits, then device complexity is reduced, but memory density and spatial efficiency deteriorate
Solution Approach 1:
The patent divides the memory array into two distinct segments: first memory structures with a single memory element per transistor for MSBs, and second memory structures with multiple memory elements per transistor for LSBs. This segmentation allows each segment to be optimized for its specific function, achieving both simplified control for MSBs and high density for LSBs.
Solution Approach 2:
The patent applies different memory structure configurations to different parts of the memory array based on local requirements. MSB positions use single-memory-element structures with simpler control, while LSB positions use multiple-memory-element structures with higher density. This local differentiation optimizes overall system performance by matching structure complexity to functional requirements.
2Quantity of substance
If multiple-memory-element structures are used for all bits, then memory density is increased, but device complexity and power consumption increase
Solution Approach 1:
The patent segments the memory array so that only the portion storing LSBs uses multiple-memory-element structures, while the portion storing MSBs uses simpler single-memory-element structures. This reduces the overall number of complex structures needed while maintaining high density where it matters most for capacity.
Solution Approach 2:
Multiple-memory-element structures are applied locally only to LSB positions where high density is critical, rather than uniformly across the entire array. This localized application minimizes the total complexity and power consumption while achieving the required memory capacity.
3Reliability
If more transistors are used per memory element, then reliability is improved, but spatial efficiency and memory density deteriorate
Solution Approach 1:
The patent segments the memory array into two types of memory structures with different transistor-to-memory-element ratios. First memory structures have a ratio optimized for reliability with simpler control, while second memory structures have a higher ratio optimized for density. This segmentation allows each segment to achieve its reliability target without unnecessarily increasing overall area.
Solution Approach 2:
Different transistor-to-memory-element ratios are applied locally to different memory structures based on their specific requirements. MSB positions use configurations optimized for reliability, while LSB positions use configurations optimized for density. This local optimization achieves system-level reliability without uniformly increasing area consumption.
Data Source
AI summary
In some aspects of the present disclosure, a memory array structure is disclosed. In some embodiments, the memory array structure includes a word array. In some embodiments, the word array stores an N-bit word. In some embodiments, the word array includes a plurality of first memory structures and a plurality of second memory structures. In some embodiments, each first memory structure includes a first transistor and a first memory element. In some embodiments, each second memory structure includes a second transistor and a plurality of second memory elements, each second memory element includes a first end and a second end, the first end of each second memory element is coupled to a corresponding bit line, and the second end of each second memory element is coupled to a first end of the second transistor.