Memory Bank Transfer Bus for Parallel Low-Power Data Movement
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Solution Overview
Problem
Existing memory devices face inefficiencies in data transfer between banks, leading to increased power consumption and processing time, as they often rely on external buses and sequential data transfer methods.
Innovation Solution
The implementation of a bank-to-bank transfer (BBT) bus that allows for parallel, optimized data transfer between memory banks without using external buses, utilizing a separate internal bus for efficient data movement within the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If data transfer between memory banks uses external buses, then device complexity is reduced, but processing time increases and power consumption increases
Solution Approach 1:
The patent introduces a new internal BBT bus dimension within the memory device that operates independently from external buses. This internal transfer path allows parallel data movement between banks without increasing external interface complexity, resolving the contradiction by adding an internal dimension for fast transfer while maintaining simple external interfaces.
Solution Approach 2:
The patent segments the data transfer function into two distinct paths: external buses for device communication and an internal BBT bus for bank-to-bank transfer. This segmentation allows each path to be optimized independently, with the internal BBT bus dedicated to high-speed inter-bank communication without affecting external bus complexity.
2Device complexity
If data transfer between memory banks uses external buses, then device complexity is reduced, but power consumption increases
Solution Approach 1:
The internal BBT bus creates a new energy-efficient dimension for data transfer within the memory device. By routing bank-to-bank transfers through this internal path rather than external buses, the system reduces power consumption for internal operations while maintaining simple external bus interfaces.
Solution Approach 2:
The patent extracts the bank-to-bank transfer function from the external bus system and implements it through a dedicated internal BBT bus. This extraction separates internal high-frequency transfer operations from external communication, reducing the power burden on external buses and enabling lower overall power consumption.
3Device complexity
If sequential data transfer methods are used, then device complexity is reduced, but productivity decreases
Solution Approach 1:
The internal BBT bus enables parallel data transfer operations as a new dimension of productivity. Multiple banks can simultaneously exchange data through this internal path without interfering with external bus operations, significantly increasing throughput while keeping the external interface simple and sequential.
Solution Approach 2:
The patent segments transfer operations into sequential external bus transfers and parallel internal BBT bus transfers. This segmentation allows the system to maintain simple sequential external interfaces while achieving high productivity through parallel internal operations, effectively decoupling interface simplicity from transfer speed.
Data Source
AI summary
The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.