Symmetric Memory Cell Layout for Low-Power BNN Weight Storage
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Solution Overview
Problem
Traditional computing models face challenges in processing large-scale big data due to limited memory capacity, high input/output pressure, low cache hit rate, and low overall performance, leading to difficulties in ensuring timeliness and efficiency in data processing.
Innovation Solution
A symmetric memory cell and a BNN circuit are introduced, featuring a first and second complementary structure with control transistors and programmable diodes, allowing for efficient storage and retrieval of weight values 1 or 0, thereby reducing power consumption and eliminating the need for complex reading circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional computing centered model is used for big data processing, then data processing can be performed, but memory capacity is limited and I/O pressure is high
Solution Approach 1:
The patent transitions from traditional vertical memory expansion to a cross-layer memory hierarchy, adding the dimension of cache memory between main memory and CPU. This dimensional change in memory architecture enables faster data access without increasing main memory capacity, thereby improving data processing efficiency while maintaining limited memory resources.
Solution Approach 2:
The patent segments the memory system into multiple hierarchical levels: cache memory, main memory, and virtual memory. This segmentation allows different types of data to be stored in different memory layers based on access frequency, enabling efficient data processing by keeping frequently accessed data in faster cache memory while maintaining overall memory capacity management.
2Productivity
If traditional computing centered model is used for big data processing, then data processing can be performed, but I/O pressure is high and cache hit rate is low
Solution Approach 1:
The patent implements preliminary action by pre-loading frequently accessed data into cache memory before it is needed by the CPU. The memory management unit predicts data access patterns and proactively transfers data to faster memory layers, reducing I/O pressure and improving cache hit rate, thereby enhancing data processing efficiency while minimizing energy-consuming I/O operations.
3Measurement precision
If complex reading circuits are used in memory cells, then reading accuracy can be improved, but power consumption increases
Solution Approach 1:
The patent employs self-service mechanisms where the memory cell structure itself, with its symmetric complementary design, provides inherent reading capability. The differential voltage output from the symmetric memory cell structure enables direct reading without requiring complex external reading circuits, thereby maintaining reading accuracy while significantly reducing power consumption.
Data Source
AI summary
Provided are a symmetric memory cell and a BNN circuit. The symmetric memory cell includes a first complementary structure and a second complementary structure, the second complementary structure being symmetrically connected to the first complementary structure in a first direction, wherein the first complementary structure includes a first control transistor configured to be connected to the second complementary structure, the second complementary structure includes a second control transistor, a drain electrode of the second control transistor and a drain electrode of the first control transistor being symmetrically arranged in the first direction and connected to a bit line, and the symmetric memory cell is configured to store a weight value 1 or 0.