Resistor-Array Neural IC Without Interlayer ADC Conversion
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Solution Overview
Problem
Existing neural network implementations require analog-to-digital converters (ADCs) between successive layers, which occupy significant chip area and consume power, limiting the efficiency of data processing and transfer.
Innovation Solution
The implementation of neural networks using matrices or arrays of resistors for data propagation, allowing direct analog voltage transfer between layers without the need for ADCs, thereby reducing chip area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If ADCs are used between successive layers in neural networks, then data conversion accuracy is improved, but chip area and power consumption increase significantly
Solution Approach 1:
The patent extracts and removes the ADC component from the neural network architecture. By eliminating the ADC between successive layers and using direct analog signal transmission through resistor arrays, the patent achieves significant chip area reduction while maintaining computational functionality through alternative analog processing mechanisms.
Solution Approach 2:
The patent substitutes the mechanical/electronic ADC conversion system with an analog resistor array-based computation system. Instead of converting analog signals to digital and back, the system uses resistors to directly compute weighted sums in the analog domain, replacing the ADC mechanism with a passive analog computation approach.
2Measurement precision
If ADCs are used between successive layers in neural networks, then data conversion accuracy is improved, but power consumption increases significantly
Solution Approach 1:
The patent extracts and removes the ADC component from the neural network architecture. By eliminating the ADC between successive layers and using direct analog signal transmission through resistor arrays, the patent achieves significant chip area reduction while maintaining computational functionality through alternative analog processing mechanisms.
Solution Approach 2:
The patent substitutes the mechanical/electronic ADC conversion system with an analog resistor array-based computation system. Instead of converting analog signals to digital and back, the system uses resistors to directly compute weighted sums in the analog domain, replacing the ADC mechanism with a passive analog computation approach.
3Measurement precision
If ADCs are used between successive layers, then data processing accuracy is improved, but processing speed decreases
Solution Approach 1:
The patent enables continuous analog signal flow through the neural network layers without interruption for conversion. By maintaining uninterrupted analog transmission through resistor arrays, the system eliminates the stop-start nature of ADC conversion cycles, achieving continuous computation that improves processing speed while preserving accuracy through analog computation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster processing, reduced chip area, and lower power consumption by eliminating the need for ADCs between successive layers in neural network integrated circuits.
Implementation Method 1
a first array of resistors, a second array of resistors, and a plurality of interface circuits electrically coupled between the first array of resistors and the second array of resistors
Data Source
AI summary
An integrated circuit includes a first array of resistors, a second array of resistors, and a plurality of interface circuits electrically coupled between the first array of resistors and the second array of resistors. Each interface circuit among the plurality of interface circuits is configured to receive a signal from the first array of resistors, and apply an analog voltage corresponding to the signal to the second array of resistors.


