Memory Command Bus Training with Parity-Based CA Error Feedback
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing command bus training methods for LPDDR4 and LPDDR5 memory devices are slow and require significant firmware coordination, limiting the speed and quality of command bus training due to the need for iterative testing of CA patterns, which can miss thousands of potential sampling points and result in lengthy training times.
Innovation Solution
The implementation of a command address training mode (CATM) similar to that used in DDR5 memory devices, which simplifies error checking by using parity checks, reducing the coordination work for firmware and enabling faster and more efficient command bus training by allowing internal circuitry to handle error detection and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional iterative testing of CA patterns is used for command bus training, then error detection can be achieved, but training time becomes excessively long and firmware coordination complexity increases
Solution Approach 1:
The patent replaces the mechanical iterative testing process with an electrical signal-based error detection mechanism. The memory device samples CA patterns and returns error indicators through data bus signals, eliminating the need for repeated firmware-controlled testing cycles while maintaining error detection accuracy
Solution Approach 2:
The patent introduces data bus signals as an intermediary carrier to transmit error detection information from the memory device back to the memory controller. This intermediary mechanism enables error feedback without requiring firmware intervention, significantly reducing training time
2Measurement precision
If extensive iterative testing is performed to improve training quality, then sampling accuracy increases, but the number of firmware coordination operations increases dramatically
Solution Approach 1:
The memory device performs self-diagnosis by sampling CA patterns and automatically generating error indicators. This self-service capability eliminates the need for complex firmware coordination, as the memory device independently completes error detection and communicates results through standardized data bus signals
Solution Approach 2:
The patent extracts the error detection function from the firmware coordination process and implements it within the memory device's internal circuitry. This separation removes the burden of extensive firmware operations while preserving sampling accuracy through dedicated sampling circuits
3Adaptability or versatility
If traditional training methods are used, then compatibility with existing protocols is maintained, but training speed and efficiency are limited
Solution Approach 1:
The patent makes the data bus serve multiple functions: it carries both normal data transactions and error detection feedback signals. This multi-functionality allows the implementation of faster training procedures without requiring additional dedicated signal lines, thus maintaining protocol compatibility while improving training speed
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Techniques for command bus training to a memory device includes triggering a memory device to enter a first or a second command bus training mode, outputting a command/address (CA) pattern via a command bus and compressing a sampled CA pattern returned from the memory device based on whether the memory device was triggered to be in the first or the second command bus training mode.