1T DRAM Buffer Memory for Unified Controller Integration
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Solution Overview
Problem
Conventional memory systems require multiple controllers for different types of non-volatile and volatile memory devices, leading to inefficiencies in size, power consumption, and cost due to the need for various interfaces, and the use of DRAM with capacitors limits high integration in semiconductor memory devices.
Innovation Solution
Implementing a 1T DRAM as a buffer memory with a floating body, eliminating the need for capacitors and allowing a unified DRAM interface for all memory devices, which reduces the size and complexity of memory systems by using a single controller for multiple non-volatile memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DRAM with capacitors is used as buffer memory, then data storage capability is improved, but device area and integration density deteriorate
Solution Approach 1:
The patent extracts and removes the capacitor component from the traditional DRAM cell structure, retaining only the transistor. This extraction eliminates the need for large-area capacitor structures while maintaining data storage functionality through alternative mechanisms (such as charge trapping in the transistor body or gate), thereby resolving the contradiction between data storage capability and device area.
Solution Approach 2:
The patent changes the fundamental operating parameters of the DRAM cell by transitioning from a capacitor-based charge storage mechanism to a transistor-based mechanism (such as body effect or threshold voltage modulation). This parameter change enables data storage without requiring the physical capacitor structure, thus improving integration density while maintaining functionality.
2Adaptability or versatility
If multiple controllers are used for different memory devices, then interface compatibility is improved, but system complexity and cost deteriorate
Solution Approach 1:
The patent implements a universal controller design that can interface with multiple types of memory devices (including the new capacitor-less DRAM, NAND flash, and other non-volatile memories) through a single unified interface. This universal controller performs multiple functions and adapts to different memory types, eliminating the need for separate dedicated controllers for each memory type, thereby reducing system complexity while maintaining interface compatibility.
Solution Approach 2:
The patent segments the control functionality into modular components that can be selectively activated based on the connected memory device type. This segmentation allows a single controller to handle different memory protocols and interfaces through modular control logic, reducing overall system complexity while maintaining adaptability to various memory devices.
Data Source
AI summary
A non volatile memory device and a memory system having the same are disclosed. The non volatile memory device may include a memory cell array having a plurality of non volatile memory cells, a DRAM interface for exchanging data, a command and an address with an external device, a controller for selecting one of the memory cells in response to the address and performing a control operation for one of outputting data of the selected memory cell to the external device in response to the command and storing data received from the external device, and a DRAM buffer memory. The DRAM buffer memory has dynamic memory cells, and each of the dynamic memory cells has one transistor with a floating body.