1T2R Resistive Memory Cell Structure for High Density
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Solution Overview
Problem
Conventional random-access memory (RAM) cells require 6 transistors per cell, limiting memory cell density in field programmable gate arrays (FPGAs) and are volatile, susceptible to data loss due to power loss and radiation effects.
Innovation Solution
A 1T2R resistive random-access memory cell structure is developed, comprising a standard transistor with two resistive RAM element stacks, where the anodes of both stacks are connected to the gate terminal, and a dielectric isolation layer with vias exposing the gate terminal, allowing for reduced area usage and non-volatile memory storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 6-transistor RAM cells are used, then data storage capability is achieved, but memory cell density is limited
Solution Approach 1:
The patent combines two RRAM elements with a single transistor to form a 1T2R memory cell, merging the storage function of two resistive elements with one transistor control unit. This integration reduces the total component count from 6 transistors (conventional RAM) to 1 transistor plus 2 RRAM elements, thereby increasing memory cell density while maintaining data storage capability.
Solution Approach 2:
The patent replaces the charge-based memory mechanism (transistor charge storage) with a resistive-based mechanism (RRAM element resistance states). This substitution uses physical resistance changes rather than electrical charge retention, enabling non-volatile storage and reducing the number of transistors needed per memory cell.
2Reliability
If conventional RAM cells are used, then data storage is achieved, but volatility makes data loss occur when powered off
Solution Approach 1:
The patent changes the fundamental storage parameter from electrical charge (volatile) to electrical resistance (non-volatile). The RRAM elements maintain their resistance states without power, transforming the memory from volatile to non-volatile by altering the physical state parameter used for data storage.
Solution Approach 2:
The patent employs RRAM elements that can be easily programmed and reset, using simple resistance switching mechanisms rather than complex charge trapping structures. This approach uses simpler, more durable components that don't require continuous power to maintain state, improving reliability without increasing complexity.
3Object-affected harmful factors
If conventional RAM cells are used, then memory function is achieved, but susceptibility to radiation effects causes data loss
Solution Approach 1:
The patent replaces charge-based storage (susceptible to radiation-induced charge loss) with resistance-based storage (more radiation-hardened). The RRAM elements use physical resistance changes that are less susceptible to radiation effects, improving data integrity in radiation environments while maintaining memory functionality.
4Quantity of substance
If 1T2R structure is implemented, then memory cell density increases, but area requirements for vias and isolation layers increase
Solution Approach 1:
The patent transitions from planar 2D layout to 3D vertical stacking by placing RRAM elements in vias through the isolation layer. This dimensional change allows memory components to be arranged vertically rather than only horizontally, increasing storage density without proportionally increasing the die area footprint.
Solution Approach 2:
The patent nests the RRAM elements within the isolation layer structure by forming vias through the isolation layer and placing switching layers and electrodes within these vias. This nesting approach efficiently utilizes the vertical space above the transistor gate, accommodating additional memory components without significantly expanding the horizontal cell area.
Data Source
AI summary
Resistive random-access memory cell structures including a first and second resistive random-access memory element stacks, each including an anode and a cathode; a pass transistor having first and second source/drain terminals, and a gate terminal. The gate terminal is connected to the anodes of the first and second resistive random-access memory element stacks. An isolation layer is disposed upon the gate terminal. The isolation layer includes at least two vias, each defined by a perimeter extending from a top surface of the isolation layer to a bottom surface of the isolation layer, each perimeter exposes a portion of the gate. The first and second resistive random-access memory element stacks include a bottom electrode, a switching layer, a top electrode and a low-resistance film. The gate is the bottom electrode. The switching layer, top electrode and low resistance film are disposed in the vias.